Synthesis > Synopsys(DC)

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all_clocks

NAME all_clocks Returns a collection of all clocks in the current design.
SYNTAX collection all_clocks
ARGUMENTS This command has no arguments.
DESCRIPTION Returns a collection containing all clocks in the current design. The clocks must be defined in the design before running this command. T ...
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all_inputs

NAME all_inputs Returns a collection of input or inout ports in the current design.
SYNTAX collection all_inputs [-clock clock_name] [-edge_triggered | -level_sensitive] Data Types clock_name string
ARGUMENTS -clock clock_name Limits the ...
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all_outputs

NAME all_outputs Returns a collection of output or inout ports in the current design.
SYNTAX collection all_outputs [-clock clock_name] [-edge_triggered | -level_sensitive] Data Types clock_name string
ARGUMENTS -clock clock_name Limits t ...
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create_clock

NAME create_clock Creates a clock object and defines its waveform in the current design.
SYNTAX status create_clock [-name clock_name] [-add] [source_objects] [-period period_value] [-waveform edge_list] Data Types clock_nam ...
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create_generated_clock

NAME create_generated_clock Creates a generated clock object.
SYNTAX string create_generated_clock [-name clock_name] [-add] source_objects -source master_pin [-master_clock clock] [-divide_by divide_factor | -multiply_by ...
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current_design

NAME current_design Sets the working design.
SYNTAX string current_design [design] Data Types design string
ARGUMENTS design Specifies the working or focal design for many dc_shell com- mands. If design is not specified or a period "." is specified, d ...
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get_cells

NAME get_cells Creates a collection of cells from the current design, relative to the current instance.
SYNTAX collection get_cells [-hierarchical] [-quiet] [-regexp] [-nocase] [-exact] [-filter expression] [ ...
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get_clocks

NAME get_clocks Creates a collection of clocks from the current design.
SYNTAX collection get_clocks [-quiet] [-regexp] [-nocase] [-filter expression] patterns Data Types expression string patterns list
ARGUMENTS -q ...
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get_lib_cells

NAME get_lib_cells Creates a collection of library cells from the libraries loaded into memory.
SYNTAX collection get_lib_cells [-filter expression] [-quiet] [-regexp] [-nocase] [-exact] [-scenario scenario_name] ...
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get_lib_pins

NAME get_lib_pins Creates a collection of library cell pins from libraries loaded into memory.
SYNTAX collection get_lib_pins [-filter expression] [-quiet] [-regexp] [-nocase] [-exact] patterns | -of_objects objects Da ...
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get_libs

NAME get_libs Creates a collection of libraries loaded into memory.
SYNTAX collection get_libs [-filter expression] [-quiet] [-regexp] [-nocase] [-exact] [-scenario scenario_name] [-of_objects objects] [patter ...
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get_nets

NAME get_nets Creates a collection of nets that meet the specified criteria.
SYNTAX collection get_nets [-hierarchical] [-filter expression] [-quiet] [-regexp] [-nocase] [-exact] [-top_net_of_hierarchical_group] ...
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get_pins

NAME get_pins Creates a collection of pins that match the specified criteria.
SYNTAX collection get_pins [-hierarchical] [-filter expression] [-quiet] [-regexp [-nocase] | -exact] [patterns | -of_objects objects [-leaf]] Data Types express ...
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get_ports

NAME get_ports Creates a collection of ports from the current design.
SYNTAX collection get_ports [-quiet] [-regexp] [-nocase] [-exact] [-filter expression] patterns | -of_objects objects [-hierarchical] Data Types ...
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set_case_analysis

NAME set_case_analysis Specifies that a port or pin is at a constant logic value 1 or 0, or is considered with a rising or falling transition..
SYNTAX string set_case_analysis value port_or_pin_list Data Types port_or_pin_list list
ARGUMENTS value 0 | 1 ...
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set_clock_gating_check

NAME set_clock_gating_check Puts setup and hold checks on clock gating cells.
SYNTAX int set_clock_gating_check [-setup setup_margin] [-hold hold_margin] [-rise] [-fall] [-high | -low] [object_list] Data Types setup_margin ...
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set_clock_latency

NAME set_clock_latency Specifies clock network latency.
SYNTAX string set_clock_latency [-rise] [-fall] [-min] [-max] [-source] [-early] [-late] [-clock clock_list] delay object_lis ...
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set_clock_transition

NAME set_clock_transition Sets clock transition attributes on clock objects.
SYNTAX int set_clock_transition transition [-rise | -fall] [-min] [-max] clock_list Data Types transition float clock_list list
ARGUMENTS tr ...
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set_clock_uncertainty

NAME set_clock_uncertainty Specifies the uncertainty (skew) of specified clock networks.
SYNTAX string set_clock_uncertainty [object_list | -from from_clock | -rise_from rise_from_clock | -fall_from fall_from_clock -to to_clock | ...
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set_data_check

NAME set_data_check Sets data-to-data checks using the specified values of setup and hold time.
SYNTAX string set_data_check -from from_object | -rise_from from_object | -fall_from from_object -to to_object | -rise_to to_object ...
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set_disable_timing

NAME set_disable_timing Disables timing arcs in the current design.
SYNTAX int set_disable_timing object_list [-from from_pin_name -to to_pin_name] [-restore] Data Types object_list list from_pin_name string to_pin_name string
ARGUMENTS ...
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set_drive

NAME set_drive Sets the rise_drive or fall_drive attributes to specified resis- tance values on specified input and inout ports.
SYNTAX int set_drive resistance [-rise] [-fall] [-min] [-max] port_list Data Types resistance float port_list ...
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set_driving_cell

NAME set_driving_cell Sets attributes on input or inout ports of the current design, specifying that a library cell or pin drives ports.
SYNTAX int set_driving_cell [-lib_cell lib_cell_name] [-library lib] [-rise] [-fall] [-min] ...
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set_false_path

NAME set_false_path Removes timing constraints from particular paths.
SYNTAX int set_false_path [-rise | -fall] [-setup | -hold] [-from from_list | -rise_from rise_from_list | -fall_from fall_from_list] [-through through_list] [-rise ...
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set_fanout_load

NAME set_fanout_load Sets the fanout_load attribute to a specified value on specified output ports of the current design.
SYNTAX int set_fanout_load value port_list Data Types value float port_list list
ARGUMENTS value Specifies the value t ...
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set_input_delay

NAME set_input_delay Sets input delay on pins or input ports relative to a clock sig- nal.
SYNTAX status set_input_delay delay_value [-clock clock_name] [-clock_fall] [-level_sensitive] [-network_latency_included] [-source_ ...
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set_input_transition

NAME set_input_transition Sets the max_transition_rise, max_transition_fall, min_transi- tion_rise, or min_transition_fall attributes to the specified transition values on the specified input and inout ports.
SYNTAX int set_input_transition transition [-rise] ...
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set_load

NAME set_load Sets the load attribute to a specified value on specified ports and nets.
SYNTAX status set_load value objects [-subtract_pin_load] [-min] [-max] [[-pin_load] [-wire_load]] Data Types value f ...
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set_logic_dc

NAME set_logic_dc Specifies one or more input ports in the current design that are to be driven by don't care. The set_logic_one and set_logic_zero commands are used the same way as this command.
SYNTAX int set_logic_dc port_list Data Types port_list ...
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set_logic_one

NAME set_logic_one Specifies one or more input ports in the current design that are to be driven by logic one. The set_logic_zero and set_logic_dc commands are used the same way as this command.
SYNTAX int set_logic_one port_list Data Types port_list list ARGUM ...
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set_logic_zero

NAME set_logic_zero Specifies one or more input ports in the current design that are to be driven by logic zero. The set_logic_one and set_logic_dc commands are used the same way as this command.
SYNTAX int set_logic_zero port_list Data Types port_list list ARG ...
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set_max_area

NAME set_max_area Sets the max_area attribute to a specified value on the current design.
SYNTAX int set_max_area [-ignore_tns] area_value Data Types area_value float
ARGUMENTS -ignore_tns Specifies that the area is prioritized above tot ...
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set_max_capacitance

NAME set_max_capacitance Sets the max_capacitance attribute to a specified value on the specified input ports and designs.
SYNTAX int set_max_capacitance capacitance_value object_list
ARGUMENTS capacitance_value Specifies a value to which the max_capacita ...
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set_max_delay

NAME set_max_delay Specifies a maximum delay target for paths in the current design.
SYNTAX int set_max_delay delay_value [-rise | -fall] [-from from_list | -rise_from rise_from_list | -fall_from fall_from_list] ...
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set_max_dynamic_power

NAME set_max_dynamic_power Sets the target dynamic power for the current design by setting the max_dynamic_power attribute to a specified value.
SYNTAX int set_max_dynamic_power dynamic_power [GW | MW | KW | W | mW | uW | nW | pW | fW | aW] Data Types dynamic_power ...
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set_max_fanout

NAME set_max_fanout Sets the max_fanout attribute to a specified value on specified input ports and/or designs.
SYNTAX int set_max_fanout fanout_value object_list
ARGUMENTS fanout_value Specifies the value to which the max_fanout attribute is to be ...
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set_max_leakage_power

NAME set_max_leakage_power Sets the target leakage power for the current design by setting the max_leakage_power attribute to a specified value.
SYNTAX int set_max_leakage_power leakage_power [GW | MW | KW | W | mW | uW | nW | pW | fW | aW] Data Types leakage_power ...
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set_max_time_borrow

NAME set_max_time_borrow Sets the max_time_borrow attribute to a specified value on clocks, latch cells, data pins, or clock (enable) pins, to con- strain the amount of time borrowing possible for level-sensitive latches.
SYNTAX int set_max_time_borrow delay ...
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set_max_transition

NAME set_max_transition Sets the max_transition attribute to a specified value on speci- fied clocks group, ports or designs.
SYNTAX int set_max_transition transition_value object_list
ARGUMENTS transition_value Specifies a maximum transition time for th ...
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set_min_capacitance

NAME set_min_capacitance Sets the min_capacitance attribute to a specified value on spec- ified input ports in the current design.
SYNTAX int set_min_capacitance capacitance_value object_list Data Types capacitance_value float object_list list AR ...
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set_min_delay

NAME set_min_delay Specifies a minimum delay target for paths in the current design.
SYNTAX int set_min_delay delay_value [-rise | -fall] [-from from_list | -rise_from rise_from_list | -fall_from fall_from_list] ...
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set_multicycle_path

NAME set_multicycle_path Modifies the single-cycle timing relationship of a constrained path.
SYNTAX integer set_multicycle_path path_multiplier [-rise | -fall] [-setup | -hold] [-start | -end] [-from from_list | -rise_ ...
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set_operating_conditions

NAME set_operating_conditions Defines the operating conditions for the current design.
SYNTAX int set_operating_conditions [-analysis_type bc_wc | on_chip_variation] [-min min_condition] [-max max_condition] [-min_library min_lib] [-max_library max_li ...
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set_output_delay

NAME set_output_delay Sets output delay on pins or output ports relative to a clock signal.
SYNTAX int set_output_delay delay_value [-clock clock_name [-clock_fall] [-level_sensitive]] [-network_latency_included] [-source_latency_included] ...
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set_port_fanout_number

NAME set_port_fanout_number Sets the number of external fanout points driven by specified ports in the current design.
SYNTAX status set_port_fanout_number fanout_number port_list Data Types fanout_number float port_list list
ARGUMENTS fa ...
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set_propagated_clock

NAME set_propagated_clock Specifies propagated clock latency.
SYNTAX string set_propagated_clock object_list Data Types object_list list
ARGUMENTS object_list Provides a list of clocks, ports, pins, or cells.
DESCRIPTION Specifies that delays be propagated throu ...
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set_resistance

NAME set_resistance Sets the resistance value on nets.
SYNTAX int set_resistance value [-min] [-max] net_list Data Types value float net_list list
ARGUMENTS value Specifies the resistance value for nets in net_list. value must be expressed ...
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set_wire_load_min_block_size

NAME set_wire_load_min_block_size Sets the wire load min_block_size attribute on the current design.
SYNTAX int set_wire_load_min_block_size size Data Types size float
ARGUMENTS size A positive value in the units of the technology library, that ...
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set_wire_load_mode

NAME set_wire_load_mode Sets the wire_load_model_mode attribute on the current design, specifying how wire load models are to be used to calculate wire capacitance in nets.
SYNTAX status set_wire_load_mode mode_name Data Types mode_name string
ARGUMENTS ...
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set_wire_load_model

NAME set_wire_load_model Sets the wire_load_attach_name attribute on designs, ports, hierarchical cells of current design, for selecting a wire load model to use in calculating wire capacitance.
SYNTAX status set_wire_load_model -name model_name [-library lib ...
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set_wire_load_selection_group

NAME set_wire_load_selection_group Specify a selection group to use for determining a wire load model to be assigned to designs and cells or to a specified cluster. This command is supported only for the enclosed wire load mode.
SYNTAX int set_wire_load_selection_gro ...
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