System Interconnect Is The Center of an AI SoC
AI SoC involves intensive data communication
Interconnect is at the center of an SoC
Critical to system performance
Longest physical connections between cells
Impact on wire routing congestion
Critical in modern data driven processing
Power-disconnect logic conserves energy
Ad-hoc patterns make analysis a non-trivial task
Features of MPA for AI SoC
Detail Trace of System Interconnect
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End-to-end data trace across bus protocols and memory hierarchy
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Pin-point current bottleneck or potential performance pitfalls
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Provide design guidelines
Detail Memory Efficiency Analysis
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Return detail of memory usage patterns
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Analyze memory level parallelism, data access locality
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Provide optimization suggestions
Comprehensive Performance Analysis of AI SoC
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CPU ←→ DLA ←→ SRAM ←→ DRAM ←→ Storage
Challenges of Current Tools / Design Environments
High cost of
heavy weighted
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Usually a bundle package with high charge
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Users end up with a fat package of many gears not-needed in a project
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Heavy-weighted toolset requires steep learning curve, lengthy and intensive training to be skillful
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Fixed functions with constrained usage/analysis
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Poor support on custom features
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Agnostic to AI-related data patterns
No complete trace
of a transaction
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Isolated analysis on a single bus domain
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Require extra engineering effort to trace transaction between IPs at different bus domain
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No comprehensive trace to data access behavior in memory hierarchy
