Cold Wallet Total solution By Quotes None 200 MHz None 2018/11/18
This Cold Wallet Total solution can decrease timing for developing. Single chip solution. Include software solution for Bitcoin transaction. Secure Element  32 bit MCU Crypto Engine Hardware DSE USB2.0 device CRC calculation unit   Application :  Cold Wallet    Introduction
PLL with Multiple Output Frequency By Quotes 40.000 K μm^2 12.156 MHz 130 nm 2018/10/26
  The PLL is a 0.13μm Phase-Locked Loop (PLL) cell that provides a clock multiplier that can generate a stable 48M/96M/120MHz/156MHz clock from a 12MHz clock source.  This is a “generic” PLL which integrates the Voltage-Controlled Oscillator (VCO), Phase-Frequency Detector, Low Pass Filter, Loop Divider and Post Divider.   This PLL provides an operating voltage range of 1.08V ~ 1.32V, and an operating junction temperature range of -40˚ ~ 125℃.  Introduction
4.2V-to-1.8V DC/DC Converter By Quotes 40.000 K μm^2 1 Hz 130 nm 2018/10/22
  The DCDC18 is a 0.13μm DC to DC converter in buck mode cell that converters input voltage to a smaller output voltage. The output voltage can be programmed from 1.65V to 1.9V.An external 10uH inductor is necessary.  Introduction
4.2V-to-1.2V DC/DC Converter By Quotes 40.000 K μm^2 1 MHz 130 nm 2018/10/18
The DCDC12 is a 0.13μm DC to DC converter in buck mode cell that converters input voltage to a smaller output voltage. The output voltage can be programmed from 1.05V to 1.3V.An external 10uH inductor is necessary. Introduction
0.13um Real Time Clock By Quotes None 32 KHz 130 nm 2018/10/17
The RTC is a 0.13μm Real-Time-Clock cell that provides multiple clocks.   This RTC provides an operating voltage range of 2.7V ~ 3.3V, and an operating junction temperature range of -40˚ ~ 125℃. Introduction
10-Bit 1MSPS Cyclic A/D Converter By Quotes 300.000 K μm^2 10.12 MHz 250 nm 2018/10/12
This IP is a 1MSPS , single supply , 10-bit analog-to-digital converter (ADC) that combines a low cost, high speed CMOS process and a novel architecture. It is a complete ADC with an on chip, high performance sample-and-hold amplifier and voltage reference. An external reference can be chosen to suit the dc accuracy and temperature drift requirements of the application. The device uses a cyclic architecture with digital error correction logic to guarantee no missing code over the full operating range. The input of this ADC is highly flexible. A truly differential input structure allows for both single-ended and differential input interface of varying span. The sample-and-hold amplifier (SHA) is equally suited for multiplexed systems that switched full-scale voltage levels in successive channels as well as sampling single-channel inputs at frequencies up to and beyond the Nyquist rate of 500KHz. Introduction
Chroma Resampler By Quotes None 400 MHz None 2018/01/11
The IP Core is a fully pipelined chroma resampler that converts pixels between 4:4:4 and 4:2:2 formats in the YCbCr colour space. In total, the IP Core package contains two distinct modules – one module that converts from 4:4:4 to 4:2:2 and the other that performs the reciprocal operation from 4:2:2 to 4:4:4. Pixels flow into the design in accordance with the valid ready pipeline protocol. Input pixels and syncs are sampled on the rising edge of clk when PIX_VALID and PIX_READY are both high. At the output interface, pixels and syncs are sampled on a the rising edge of clk when POUT_VALID and POUT_READY  are high. The input and output sync signals are coincident with the first pixel of a frame and the first pixel of a line.  These are useful to identify the video frame and line boundaries.  Application Digital video and image processing Interfacing between different video processing and video transceiver ICs that use different colour formats Introduction
Multi-format Video Deinterlacer By Quotes None 200 MHz None 2018/01/11
The IP Core is a high quality 24-bit RGB video deinterlacer capable of generating progressive output video at up to 4096x4096 pixels in resolution. The design is fully customizable, supporting any desired interlaced video format. The deinterlacer allows for three possible filter algorithms - either BOB, ELA  or  LCI. All three methods are 'intra-field' methods that perform spatial filtering within the same field.  For this reason, the output video is not subject to combing or tearing which is characteristic of a traditional 'weave' approach. Each algorithm has it relative merits in terms of image quality and hardware complexity. In particular, the enhanced LCI algorithm provides excellent all-round performance with reduced image softening and crisp clean edges.    Application Conversion of 'legacy' SDTV formats to HDTV video formats Generating progressive RGB video via inexpensive PAL/NTSC decoder chips High-quality video de-interlacing without the overhead of a frame buffer Digital TV set-top boxes and home media solutions Introduction
Video Interlacer By Quotes None 500 MHz None 2017/12/15
The IP Core is a fully pipelined video interlacer solution that converts any progressive video format into it's interlaced equivalent. Each interlaced output field will have half the number of lines as an input frame. The input and output interfaces are streaming interfaces that follow a simple valid-ready pipeline protocol. Input pixels and syncs are sampled on the rising edge of clk when P_VALID and  P_READY  are both high. Likewise, output pixels and syncs are sampled on the rising edge of clk when PO_VAL and PO_READY are high. Note that if no flow control is required in the design and the output is guaranteed to accept pixels without stalling, then the signal  PO_READY may be tied high and the signal  P_READY may be ignored. Application Video solutions for flat panel displays, portable devices, video consoles, video format converters, set-top boxes, digital TV etc. Conversion of all standard and custom video formats such as 1920x1080p to 1920x1080i, 720x480p to 720x480i etc. Introduction
Motion-adaptive Video Deinterlacer By Quotes None 200 MHz None 2017/12/15
The IP Core is a studio quality 24-bit RGB video deinterlacer capable of generating progressive output video at any resolution up to 216 x 216  pixels. The design is fully programmable and supports any desired interlaced video format. The design allows for three possible deinterlacing schemes. These are: weave, bilinear interpolation or motion-adaptive interpolation. The weave approach applies no filtering and may be useful to obtain a 'raw' interlaced format for subsequent processing. The other two methods are classed as 'inter-field' interpolation methods as spatial filtering is performed between both odd and even fields to achieve a clean and progressive output. The relative merits and disadvantages of each scheme are discussed further into the document. The deinterlacer core features a fully integrated video frame buffer. This buffer is completely 'elastic' and will dynamically skip and/or repeat frames depending on the input and output frame rates. All frame buffer management is handled internally with the provision of a simple memory interface for storing odd and even fields off-chip. The memory interface is 128-bits wide and is completely  generic. All memory transfers are sequential bursts of N x 128-bit words and may be adapted for connection to a variety of memory types such as SDRAM, DDR2 or DDR3. Application Digital TV set-top boxes. Industrial imaging. Automotive, home and personal media solutions Conversion of 'legacy' SDTV formats to HDTV video formats Generating progressive RGB video via inexpensive PAL/NTSC decoder chips Studio-quality video de-interlacing Introduction
μIP Price Logic Gate Count Clock Rate Technology Released Date Ratings

 1  2  3  4  5  6  7  8  9