This JPEG decompression IP core supports the Baseline Sequential DCT and Extend- ed Sequential DCT modes of the ISO/IEC 10918-1 standard. It implements a scalable, ultra-high-performance, ASIC or FPGA, hardware JPEG decoder that handles extreme- ly high pixel rates.
The JPEG-ST-V Decoder decompresses JPEG images and the video payload for Mo- tion-JPEG container formats. It accepts compressed streams of images with 8- or 12-bit color samples and up to four color components, in all widely-used color subsampling formats.
Depending on its configuration, the decoder processes from two to 32 color samples per clock cycle. Its high throughput capabilities are best exploited when decompressing streams produced by the JPEG-MT-V Encoder Core. This Encoder-Decoder pair pro- vide an extremely cost effective solution for streaming or archiving UHD (4K/8K) video, or very high frame rates at lower resolutions.
Once programmed, the easy-to-use decoder operates on a standalone basis, parsing marker segments and decompressing coded data with no assistance from a host pro- cessor. The decoder reports the image format (i.e., resolution, subsampling format, and color sample-depth) to the system, so that the decoded images are properly further processed and/or displayed.
This JPEG compression IP core supports the Baseline Sequential DCT and the Ex- tended Sequential DCT modes of the ISO/IEC 10918-1 standard. It implements a scalable, ultra-high-performance, ASIC or FPGA, hardware JPEG encoder that can compress high pixel rate video using significantly fewer silicon resources and less pow- er than encoders for video compression standards such as HEVC/H,265, DSC, AVC/H.264, or JPEG200.
The JPEG-MT-V Encoder produces compressed JPEG images and the video payload for Motion-JPEG container formats. It accepts images with up to 12-bit color samples and up to four color components, in all widely-used color subsampling formats.
Depending on its configuration, the encoder processes from two to 32 color samples per clock cycle, enabling it to compress UHD (4K/8K) video and/or very high frame vid- eo.
Once programmed, the easy-to-use encoder requires no assistance from a host pro- cessor to compress an arbitrary number of frames. SoC integration is straightforward thanks to standardized AMBA® interfaces: AXI Streaming for pixel and compressed da- ta, and a 32-bit APB slave interface for registers access. Users can optionally insert timestamps or other metadata in the compressed stream using a dedicated AXI Stream- ing interface.
This JPEG Decoder IP core has been developed to be a complete standards compliant JPEG / MJPEG Hardware Decompressor / Decoder.
When decoding JPEG images, pixel throughput can not be fixed for compressed JPEGs of arbitrary quality, as it depends on the compression ratio (bits needed to encode one pixel).
To circumvent this limitation JPEG Decoder IP features a dual pixel component pipeline, allowing for greater decoding speeds.
This IP core has been developed to be a complete standards compliant JPEG / MJPEG Hardware Compressor / Encoder.
The data interfaces in the JPEG Encoder IP Core (JPEGE) use the AXI industry standard. The Master I/O data interfaces use an AXI3 bus, forward compatible with AXI4 interconnects.
In order to let you assess the properties of the on-the-fly selectable quality setting, please use the slider below the image in order to see the final compressed image and compression ratio.
The JPEG Encoder IP Core has a real throughput of two compressed pixels every three clock cycles at any compression ratio for a chroma subsampling of 4:2:0. To calculate the throughput for your platform.