Triple 10-bit 330 MSPS Video DAC IP in TSMC 90 nm By Quotes 330.000 μm^2 330 MHz 90 nm 2019/11/28
MIC_DAC10X3 is a 10-bit Triple DAC designed in TSMC 90 nm logic process. It consists of a current steering DAC. The DAC uses a fully differential architecture. The input data of the DAC is in 1.2 V, in unsigned format. Introduction
PCI Express Gen4 PHY IP in 28nm HPC+ By Quotes None 16 Hz 28 nm 2019/11/08
The Phison Peripheral Component Interconnect Express (PCIe) x4 PHY is compliant with PCIe 4.0 Base Specification with support of PIPE v4.4 inter- face spec. Lower power consumption is achieved due to support of addition- al PLL control, reference clock control, and embedded power gating control. Also, since aforementioned low power mode setting is configurable, the PHY is widely applicable for various scenarios under different consideration of power consumption. Introduction
PCI Express Gen4 PHY IP in TSMC 12nm FFC By Quotes None 16 GHz 12 nm 2019/11/06
The Phison Peripheral Component Interconnect Express (PCIe) x4 PHY is compliant with PCIe 4.0 Base Specification with support of PIPE v4.4 inter- face spec. Lower power consumption is achieved due to support of addition- al PLL control, reference clock control, and embedded power gating control. Also, since aforementioned low power mode setting is configurable, the PHY is widely applicable for various scenarios under different consideration of power consumption. Introduction
MIPI M-PHY Gear 4 IP in TSMC 28nm HPC+ By Quotes None 11 GHz 28 nm 2019/11/04
MIPI M-PHY Gear 4 IP is compliant with the latest MIPI. Alliance M-PHY v4.1 Specification, UniPro v1.8 Specification, and Universal Flash Storage (UFS) v3.0 Specification. A serial interface technology with high bandwidth capabilities and supports HS Gear4 rates up to 11.6Gbps, which is particularly developed for mobile applications to obtain low pin count combined with very good power efficiency. The MIPI M-PHY Gear 4 IP compliant to the RMMI interface which allows UniPro controller and UFS Controller. Introduction
MIPI M-PHY Gear 4 IP in TSMC 12nm FFC By Quotes None 11 GHz 12 nm 2019/11/01
MIPI M-PHY Gear 4 IP is compliant with the latest MIPI. Alliance M-PHY v4.1 Specification, UniPro v1.8 Specification, and Universal Flash Storage (UFS) v3.0 Specification. A serial interface technology with high bandwidth capabilities and supports HS Gear4 rates up to 11.6Gbps, which is particularly developed for mobile applications to obtain low pin count combined with very good power efficiency. The MIPI M-PHY Gear 4 IP compliant to the RMMI interface which allows UniPro controller and UFS Controller. Introduction
12-Bit 320MSPS IQ DAC in IBM SOI 180nm By Quotes 254.000 K μm^2 320 MHz 180 nm 2019/10/30
MIC_DAC12X2 is compact and low power 12-bit digital-to-analog converter silicon IP in IBM 180nm SOI process. It features two channel current steering DAC. Introduction
14-Bit 1MSPS DAC in GSMC110nm By Quotes 75.000 K μm^2 1 MHz 110 nm 2019/10/29
MIC_DAC14 is compact and low power 14-bit digital-to-analog converter silicon IP. It features wide range input supply voltage from 1.7V to 5.6V. Its single-end output ranges from 0.1 to 0.9 of supply voltage. Introduction
14-Bit 3 MSPS ADC in GSMC110nm By Quotes 322.000 K μm^2 3 MHz 110 nm 2019/10/25
MCR_GS110_ADC14 is compact and low power 14-bit analog-to-digital converter silicon IP. It has 20 single-end input channel selection multiplexer or 10 differential input channels selection. This ADC uses fully differential SAR architecture optimized for low The ADC is designed for high dynamic performance for input frequencies up to Nyquist rate. Introduction
Dual-Channel 12-bit 80 MSPS ADC IP in UMC 65 nm By Quotes 450.000 μm^2 0.8 MHz 65 nm 2019/10/21
ADC X is an ultra-compact and very low power analog-to-digital converter (ADC) IP. The 12-bit 80 MSPS Dual ADC includes an internal custom bandgap voltage reference. It is capable of supplying bias currents to other parallel ADCs. IP architecture is robust and can be ported to other 65 nm processes.The ADC uses fully differential pipeline architecture with custom low-disturbance digital correction technique which allows single supply bus for both digital and analog. Introduction
12-Bit 50 MSPS ADC in IBM 180 SOI By Quotes 280.000 μm^2 50 MHz 180 nm 2019/10/18
MICIP_ADC12 is compact and low power 12-bit analog-to-digital converter silicon IP. This ADC uses 1.5b/stage pipelined architecture optimized for low power and small area. Introduction
μIP Price Logic Gate Count Clock Rate Technology Released Date Ratings

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