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14-Bit 3 MSPS ADC in GSMC110nm By Quotes 322.000 K μm^2 3 MHz 110 nm  
MCR_GS110_ADC14 is compact and low power 14-bit analog-to-digital converter silicon IP. It has 20 single-end input channel selection multiplexer or 10 differential input channels selection. This ADC uses fully differential SAR architecture optimized for low The ADC is designed for high dynamic performance for input frequencies up to Nyquist rate. Introduction
Dual-Channel 12-bit 80 MSPS ADC IP in UMC 65 nm By Quotes 450.000 μm^2 0.8 MHz 65 nm  
ADC X is an ultra-compact and very low power analog-to-digital converter (ADC) IP. The 12-bit 80 MSPS Dual ADC includes an internal custom bandgap voltage reference. It is capable of supplying bias currents to other parallel ADCs. IP architecture is robust and can be ported to other 65 nm processes.The ADC uses fully differential pipeline architecture with custom low-disturbance digital correction technique which allows single supply bus for both digital and analog. Introduction
12-Bit 50 MSPS ADC in IBM 180 SOI By Quotes 280.000 μm^2 50 MHz 180 nm  
MICIP_ADC12 is compact and low power 12-bit analog-to-digital converter silicon IP. This ADC uses 1.5b/stage pipelined architecture optimized for low power and small area. Introduction
10-Bit 1MSPS Cyclic A/D Converter By Quotes 300.000 K μm^2 10.12 MHz 250 nm  
This IP is a 1MSPS , single supply , 10-bit analog-to-digital converter (ADC) that combines a low cost, high speed CMOS process and a novel architecture. It is a complete ADC with an on chip, high performance sample-and-hold amplifier and voltage reference. An external reference can be chosen to suit the dc accuracy and temperature drift requirements of the application. The device uses a cyclic architecture with digital error correction logic to guarantee no missing code over the full operating range. The input of this ADC is highly flexible. A truly differential input structure allows for both single-ended and differential input interface of varying span. The sample-and-hold amplifier (SHA) is equally suited for multiplexed systems that switched full-scale voltage levels in successive channels as well as sampling single-channel inputs at frequencies up to and beyond the Nyquist rate of 500KHz. Introduction
8-Bit 7 GSPS SAR ADC By Quotes 300.000 K μm^2 7 GHz 16 nm  
This IP is compact and low power 8-bit Time interleaved SAR analog-to-digital converter silicon IP.This ADC uses fully differential SAR architecture optimized for low power and small silicon area.     APPLICATIONS Serdes Receiver Coherent Transceivers Data acquisition Introduction
12-Bit 800KSPS Low Power SAR-ADC By Quotes None 25 MHz 180 nm  
The SAR-ADC is a low power ADC that is implemented in Successive Approximation architecture. It can provide 12-bit resolution capability with only 3V supply voltage. It accepts an analog input range from 0 to VCC   and digitizes the input at a maximum sampling frequency rate of 800KHz at 5V supply voltage. This ADC also includes MUX design to select 0 of 7 analog inputs. The power dissipation is less than 5mW with 5V power supply. This SAR-ADC is implemented in SMIC 0.18μm generic CMOS technology. Introduction
14-Bit 3 MSPS ADC in GSMC110nm 60000 Points 32.000 K μm^2 3 MHz 110 nm  
UIP_ADC14_3M_245303  is  compact  and  low power 14-bit analog-to-digital converter silicon IP.  It  has  20  single-end  input  channel selection  multiplexer  or  10  differential  input channels  selection.  This  ADC  uses  fully differential SAR architecture optimized for low power and small area. The ADC is designed for  high  dynamic  performance  for  input frequencies  up  to  Nyquist  rate.  This  ADC consumes  150  uA  at  3  MSPS  operation  and occupies  silicon  area  of  0.32 mm2 .  The  ADC has  high  immunity  to  substrate  noise  and  is ideal  for  SoC  integration.   APPLICATIONS  General purpose data acquisition Battery monitory system  Temperature monitory system Introduction
[110nm]10-bit 80 MSPS ADC IP 60000 Points 210.000 K μm^2 80 MHz 110 nm  
UIP_ADC10_80M_183288 is an ultra-compact and very low power analog-to-digital converter (ADC) silicon IP. The 10-bit 80 MSPS ADC includes an internal custom bandgap voltage reference. It is capable of supplying bias currents to other parallel ADCs.   The ADC uses fully differential pipeline architecture with custom low-disturbance digital correction technique which allows single supply bus for both digital and analog. The ADC is designed for high dynamic performance for input frequencies up to Nyquist. This makes the IP perfectly suitable for video, imaging and communication appliances.   The IP is available in different metal options as well as deep N-well (DNW) option for SoC with high level of substrate noise. It consumes only 24mW at 80 MSPS operation and requires silicon area of 0.21 mm2. The IP does not require any external decoupling and is ideal for integration in mixed-signal systems. The output data of ADC is available in 2’s complement format.   UIP_ADC10_80M_183288 can be used in the following applications:   ‧Digital imaging ‧TV/Video ‧Wireless LAN ‧Rx communication channel Introduction
[110nm] 10-bit 165 MSPS ADC IP 70000 Points 210.000 K μm^2 165 MHz 110 nm  
UIP_ADC10_165M_213779 is an ultra-compact and very low power analog-to-digital converter (ADC) silicon IP. The 10-bit 165 MSPS ADC includes an internal custom bandgap voltage reference. It is capable of supplying bias currents to other parallel ADCs.   The ADC uses fully differential pipeline architecture with custom low-disturbance digital correction technique which allows single supply bus for both digital and analog. The ADC is designed for high dynamic performance for input frequencies up to Nyquist. This makes the IP perfectly suitable for video, imaging and communication appliances.   The IP is available in different metal options as well as deep N-well (DNW) option for SoC with high level of substrate noise. It consumes only 48mW at 165 MSPS operation and requires silicon area of 0.21 mm2. The IP does not require any external decoupling and is ideal for integration in mixed-signal systems. The output data of ADC is available in 2’s complement format.   UIP_ADC10_165M_213779 can be used in the following applications:   ‧Digital imaging ‧TV/Video ‧Wireless LAN ‧Rx communication channel ‧IOT Introduction
10-bit 80 MSPS ADC IP in 130 nm 60000 Points 210.000 K μm^2 80 MHz 130 nm  
UIP_ADC10_80M_156287 is an ultra-compact and very low power analog-to-digital converter (ADC) silicon IP. The 10-bit 80 MSPS ADC includes an internal custom bandgap voltage reference. It is capable of supplying bias currents to other parallel ADCs.   The ADC uses fully differential pipeline architecture with custom low-disturbance digital correction technique which allows single supply bus for both digital and analog. The ADC is designed for high dynamic performance for input frequencies up to Nyquist. This makes the IP perfectly suitable for video, imaging and communication appliances.   The IP is available in different metal options as well as deep N-well (DNW) option for SoC with high level of substrate noise. It consumes only 24mW at 80 MSPS operation and requires silicon area of 0.21 mm2. The IP does not require any external decoupling and is ideal for integration in mixed-signal systems. The output data of ADC is available in 2’s complement format.   UIP_ADC10_80M_156287 can be used in the following applications:   ‧Digital imaging ‧TV/Video ‧Wireless LAN ‧Rx communication channel Introduction
μIP Price Logic Gate Count Clock Rate Technology   Ratings

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