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USB 3.2 G EN 1 OTG T RANSCEIVER By Quotes None 12 MHz 28 nm  
MIP300HJ0C │ MIP300NSHJ0C_SB are USB transceivers that provide a complete range of the host and peripheral functions. They are fully compliant with the USB 3.1 Gen1 and USB 2.0 OTG specifications. In the SuperSpeed mode, this transceiver is capable of transmitting or receiving data at 5.0 Gbps. When operating in the High-Speed mode, this transceiver is capable of transmitting or receiving data at 480 Mbps. Introduction
DSP-BASED ETHERNET TRANSCEIVER in UMC 28nm HPC+ By Quotes None 25 MHz 28 nm  
A 28nm DPS-based Gigabit Ethernet transceiver. Highly intergrated 1000BASE-T, 100BASE-TX, 100BASE-FX and 10BASE-Te. Fully compliant with 100BASE-FX IEEE 802.2u standard Introduction
PCI Express Gen4 PHY IP in 28nm HPC+ By Quotes None 25 MHz 28 nm  
The Peripheral Component Interconnect Express (PCIe) x4 PHY is compliant with PCIe 4.0 Base Specification with support of PIPE v4.4 inter- face spec. Lower power consumption is achieved due to support of addition- al PLL control, reference clock control, and embedded power gating control. Also, since aforementioned low power mode setting is configurable, the PHY is widely applicable for various scenarios under different consideration of power consumption. Introduction
PCI Express Gen4 PHY IP in TSMC 12nm FFC By Quotes None 25 MHz 12 nm  
The Peripheral Component Interconnect Express (PCIe) x4 PHY is compliant with PCIe 4.0 Base Specification with support of PIPE v4.4 inter- face spec. Lower power consumption is achieved due to support of addition- al PLL control, reference clock control, and embedded power gating control. Also, since aforementioned low power mode setting is configurable, the PHY is widely applicable for various scenarios under different consideration of power consumption. Introduction
MIPI M-PHY Gear 4 IP in TSMC 28nm HPC+ By Quotes None 11 GHz 28 nm  
MIPI M-PHY Gear 4 IP is compliant with the latest MIPI. Alliance M-PHY v4.1 Specification, UniPro v1.8 Specification, and Universal Flash Storage (UFS) v3.0 Specification. A serial interface technology with high bandwidth capabilities and supports HS Gear4 rates up to 11.6Gbps, which is particularly developed for mobile applications to obtain low pin count combined with very good power efficiency. The MIPI M-PHY Gear 4 IP compliant to the RMMI interface which allows UniPro controller and UFS Controller. Introduction
MIPI M-PHY Gear 4 IP in TSMC 12nm FFC By Quotes None 11 GHz 12 nm  
MIPI M-PHY Gear 4 IP is compliant with the latest MIPI. Alliance M-PHY v4.1 Specification, UniPro v1.8 Specification, and Universal Flash Storage (UFS) v3.0 Specification. A serial interface technology with high bandwidth capabilities and supports HS Gear4 rates up to 11.6Gbps, which is particularly developed for mobile applications to obtain low pin count combined with very good power efficiency. The MIPI M-PHY Gear 4 IP compliant to the RMMI interface which allows UniPro controller and UFS Controller. Introduction
10/100/1000 Gigabit Ethernet Transceiver By Quotes None None None  
The MIPG PHY is part of the A family of devices - which includes the MIPG PHY-031, MIPG PHY-033, and the MIPG PHY. It is A company’ 4th generation, single port 10/100/1000 Mbps Tri-speed Ethernet PHY. It supports RGMII interface to the MAC.™ The MIPG PHY provides a low power, low BOM (Bill of Materials) cost solution for comprehensive applications including consumer, enterprise, carrier and home networks such as PC, HDTV, Gaming machines, Blue-ray players, IPTV STB, Mdia Players, IP Cameras, NAS, Printers, Digital Photo Frames, MoCA/Homeplug (Powerline)/EoC/ adapters and Home Router & Gateways, etc. Introduction
USB 3.0 PHY in 110nm By Quotes 1.000 M μm^2 25 MHz 110 nm  
The IP is a high speed SERDES macro which complies with USB3.0 electrical interface specification.  This macro can be easily fabricated to form multiple lanes and implemented in USB systems design, both Host and Device.The  IP is supported USB3.0 Super Speed (5Gbps) protocol and data rate. Introduction
Rapid IO PHY in 65nm By Quotes 2.295 μm^2 25 MHz 65 nm  
The IP is designed for chips that perform high bandwidth data communication while operating at low power consumption. It can also be used in any serial interface where timing and electrical specification can be satisfied. This IP has four individual Transmitter (TX) and Receiver (RX) channels, and one common phase lock loop (PLL). Introduction
USB2.0 UTMI Device PHY(non-oscillator) 100000 Points 280.000 K μm^2 30.6 MHz 40 nm  
The USB PHY is an UTMI compatible USB2.0 device PHY IP which does not  require external oscillator reference. It is comprised of both USB1.1 and USB2.0  transceivers and it is also comprised of digital logic needed to convert USB serial  data to 8 or 16 bit parallel data. Introduction
μIP Price Logic Gate Count Clock Rate Technology   Ratings

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