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  • uIP: 300 mA Capless LDO in 180 nm (VLDS0300RNM180)
  • uIP ID: 1312144353
  • μIP Type: Analog μIP
  • HDL: Verilog Behavioral Model
  • Warranty: NO
  • Simulation Tool: Cadence NC-Verilog
  • Tool Version:
  • Design Format: GDS & Schematic
  • Merge In Foundry: NO
    Designer Information
  • Member ID:1452413000700125
  • Designer Rating:
  • Feedback received:0

1. Introduction:

Noise Quencher® Capless LDO (Silicon-proven 180 nm, 300 mA, excellent supply noise rejection and fast settling)

Noise Quencher® LDOs: This series of low-power, fully-integrated low dropout (LDO) voltage regulators uses our patented Noise Quencher® Technology to provide best-in-class dynamic performance and noise rejection. The IP cores are unconditionally stable across a wide range of load currents and load capacitances and also do not require external components, thus saving package pins and valuable PC board space. These LDOs are optimized for stand-alone power management integrated circuit (PMIC) ASSPs and other analog and digital applications.

2. License Price:

By Quotes

Multiple License : NO

3. Trial Run Price:

By Quotes

4. Clock Rate:


5. Area:


6. Technology:

180 nm

7. Version: