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  • uIP: 3 mA Capless LDO in 40 nm (VLDS0003LNT040)
  • uIP ID: 1032284674
  • μIP Type: Analog μIP
  • HDL: Verilog Behavioral Model
  • Warranty: NO
  • Simulation Tool: Cadence NC-Verilog
  • Tool Version:
  • Design Format: GDS & Schematic
  • Merge In Foundry: NO
    Designer Information
  • Member ID:1452413000700125
  • Designer Rating:
  • Feedback received:0
 

1. Introduction:

Power Quencher® Capless LDO (Silicon-proven 40 nm, 3 mA, excellent quiescent current for IoT)

This series of low-power, fully-integrated low dropout (LDO) voltage regulators achieves a low-noise output voltage without external components, thus saving package pins and valuable PC board space. These LDOs are silicon-proven in a 40 nm process and are a part of our 40 nm integrated power management unit (PMU) IP core series that has been optimized for integration into Application Specific Integrated Circuits (ASICs) or Systems-on-a-Chip (SoCs), including radio frequency (RF), wireless, and narrowband Internet of Things (NB-IoT) applications.


2. License Price:

By Quotes

Multiple License : NO


3. Trial Run Price:

By Quotes


4. Clock Rate:

None


5. Area:

None


6. Technology:

40 nm


7. Version:

1.0