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  • uIP: Ultra-low Power Voltage Reference in 40 nm (VVR060LT040)
  • uIP ID: 2035491003
  • μIP Type: Analog μIP
  • HDL: Verilog Behavioral Model
  • Warranty: NO
  • Simulation Tool: Cadence NC-Verilog
  • Tool Version:
  • Design Format: GDS & Schematic
  • Merge In Foundry: NO
    Designer Information
  • Member ID:1452413000700125
  • Designer Rating:
  • Feedback received:0

1. Introduction:

Voltage Reference for Integrated PMU (Silicon-proven 40 nm, low-power for IoT with quiescent current of <0.9 μA)

This series of fully-integrated low power voltage references generates a 0.6 V output voltage and supports an input from 2.8 to 4.2 V. They operate at an ultra-low quiescent current of < 0.9 μA. These voltage references are silicon-proven in a 40 nm process and are a part of our 40 nm integrated power management unit (PMU) IP core series that has been optimized for integration into Application Specific Integrated Circuits (ASICs) or Systems-on-a-Chip (SoCs), including radio frequency (RF), wireless, and narrowband Internet of Things (NB-IoT) applications.

2. License Price:

By Quotes

Multiple License : NO

3. Trial Run Price:

By Quotes

4. Clock Rate:


5. Area:


6. Technology:

40 nm

7. Version: