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  • uIP: Octal SPI Master/Slave Controller
  • uIP ID: 345097780
  • μIP Type: Digital μIP
  • HDL: Verilog
  • Warranty: NO
  • Simulation Tool: Cadence NC-Verilog
  • Tool Version:
  • Design Format: RTL
  • Merge In Foundry: NO
    Designer Information
  • Member ID:1422368000800119
  • Designer Rating:
  • Feedback received:0
 

1. Introduction:

Designed to work with a wide variety of SPI bus variants, the core supports run-time control of several SPI protocol parameters. For example, the SPI frame width can be 1 to 4 bytes, the
most significant bit position in a frame, serial clock phase and polarity are all software- programmable. In master mode the core can control up to 32 slaves. A software controllable clock generator derives the serial clock for master mode, by dividing the frequency of a clock line dedicated for that purpose

 


2. License Price:

By Quotes

Multiple License : NO


3. Clock Rate:

500 MHz


4. Logic Gate Count:

4.641 K Gates


5. Technology:

None


6. Version:

1