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IP Mart

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  • uIP ID: 995248763
  • μIP Type: Digital μIP
  • HDL: Verilog
  • Warranty: NO
  • Simulation Tool: Cadence NC-Verilog
  • Tool Version:
  • Design Format: RTL
  • Merge In Foundry: NO
    Designer Information
  • Member ID:8161899000600443
  • Designer Rating:
  • Feedback received:0

1. Introduction:

With improvement of technology node and IC design is geting more complex, the ratio of embedded memory in SoCs have been exceeding 50%. The fault types of memory are getting complex. The Memory BIST (Built-In Self-Test) is generated for efficient controlling IC cost. The traditional BIST method is inserted along with single memory. If there are many memories in SoCs, the area and testing time of SoCs are expanded a lot due to insertion of BIST. Therefore the SoCs' cost will increase rapidly because memory testing time is too long. 
We devoted in developing SRAM testing solutions for a long time. BRAINS is based on memory testing patents to reduce testing time and increase yield rate. In addition, BRAINS has many unique features to increase SoCs' reliability and stability.

2. License Price:

50000 Points

Multiple License : YES

   - Discount for 2 ~ 5 license:10 %
   - Discount for 6 ~ 10 license:15 %
   - Discount for 11 ~ license:0 %

3. Clock Rate:

1.2 GHz

4. Logic Gate Count:

5.25 K Gates

5. Technology:

40 nm

6. Version: