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  • uIP: HEART(High Efficient Accumulative Repairing Technical)
  • uIP ID: 1196020508
  • μIP Type: Digital μIP
  • HDL: Verilog
  • Warranty: NO
  • Simulation Tool: Cadence NC-Verilog
  • Tool Version:
  • Design Format: RTL
  • Merge In Foundry: NO
    Designer Information
  • Member ID:8161899000600443
  • Designer Rating:
  • Feedback received:0
 

1. Introduction:

HEART can efficient repair faulty SRAM after using BRAINS. SoCs can mantain correctness of functions and avoid fatal error of system reault in SRAM's defect through SRAM's repairing technical.
HEART is SRAM accumulative repairing technical, and it combines advantages of Soft-repair and Hard-repair. HEART supports internal registers of SoCs and external storages of SoCs to record SRAM's faulty information. Once SoCs have new SRAM's defect after using them for a long time, users can repeated repair SRAM's defect through HEART. In addtion, HEART also support "On-Demad" testing and repairing requirement. It means that users can enable system registers of SoCs or signal of HEART to test and repair SRAM at one when SoCs have fatal error situations.

 


2. License Price:

50000 Points

Multiple License : YES

   - Discount for 2 ~ 5 license:10 %
   - Discount for 6 ~ 10 license:15 %
   - Discount for 11 ~ license:0 %


3. Clock Rate:

2.2 GHz


4. Logic Gate Count:

5.25 K Gates


5. Technology:

40 nm


6. Version:

heart_v1