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  • uIP: 32 bits RISC Microcontroller
  • uIP ID: 108073447
  • μIP Type: Digital μIP
  • HDL: Verilog
  • Warranty: YES
  • Simulation Tool: Cadence NC-Verilog
  • Tool Version:
  • Design Format: RTL
  • Merge In Foundry: NO
    Designer Information
  • Member ID:9480860000100917
  • Designer Rating:
  • Feedback received:0

1. Introduction:

The CPU Core is a 32-bit microprocessor. It has a 32-bit data path, a 32-bit register bank, and 32-bit memory interfaces. The processor has a Harvard architecture, which means that it has a separate instruction bus and data bus. This allows instructions and data accesses to take place at the same time, and as a result of this, the performance of the processor increases because data accesses do not affect the instruction pipeline.However, the instruction and data buses share the same memory space (a unified memory system). In other words, you cannot get 8 GB of memory space just because you have separate bus interfaces.


  • Wearables
  • IoT
  • Motor Control
  • Appliances
  • Connectivity
  • Smart home/building/enterprice/planet

2. License Price:

By Quotes

Multiple License : NO

3. Clock Rate:

100 MHz

4. Logic Gate Count:

33 K Gates

5. Technology:

180 nm

6. Version: