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  • uIP: FIR filter
  • uIP ID: 1670689013
  • μIP Type: Digital μIP
  • HDL: Verilog
  • Warranty: YES
  • Simulation Tool: Synopsys VCS
  • Tool Version:
  • Design Format: RTL
  • Merge In Foundry: NO
    Designer Information
  • Member ID:8920988000100487
  • Designer Rating:
  • Feedback received:0

1. Introduction:

FIR_F is an FIR filter implementation designed for very high sample rate applications.   Organized as a systolic array the filter is modular and fully scalable, permitting the user to specify large order filters without compromising maximum attainable clock-speed.  Mathematically, the filter implements the difference equation:
y[n] = h0 x[n] + h1 x[n−1] + ... + hN x[n−N ]

In the above equation, the input signal is x[n], the output signal is y[n] and h0 to hN represent the filter coefficients.  The number N is the filter order, the number of filter taps being equal to N+1.



  • General purpose FIR filters with odd or even numbers of taps
  • Filters with arbitrary sets of coefficients
  • Very high-speed filtering applications

2. License Price:

By Quotes

Multiple License : NO

3. Clock Rate:

300 MHz

4. Logic Gate Count:


5. Technology:


6. Version: