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  • uIP: RF Power Amplifier Precorrection
  • uIP ID: 433827460
  • μIP Type: Digital μIP
  • HDL: Verilog
  • Warranty: YES
  • Simulation Tool: Model-sim
  • Tool Version:
  • Design Format: RTL
  • Merge In Foundry: NO
    Designer Information
  • Member ID:5591462000500175
  • Designer Rating:
  • Feedback received:0

1. Introduction:

The IP is a complete Digital Precorrection(Predistortion) system designed to compensate for the non-linear characteristic of a high-power RF Amplifier. The system is capable of adjusting both the gain and phase of a complex input signal.   This is achieved by means of a complex multiplication of the input with a complex polynomial function stored in the LT.

The LT contains the inverse PA characteristic and is applied before the amplification stages (either at baseband or IF frequencies). By programming the LT with the inverse gain/phase PA  response,   the resultant PA response is linearized. After linearization, the output signal is much cleaner with reduced intermodulation distortion. 

The system may be used in open-loop or closed-loop configuration. For open loop operation, the LUT coefficients are static and programmed during initial setup of the PA precorrection system. For   closed-loop operation, an external circuit may compare the baseband inputs and PA outputs and adjust the LUT coefficients dynamically in order to automate the linearization process.


  • Precorrection of wide bandwidth signals such as UMTS, WCDMA and OFDM
  • Power amplifier linearization for mobile Base-stations, Broadcasting etc.
  • Precorrection of any type of digitally modulated signal where the signal envelope varies and therefore the instantaneous input power.

2. License Price:

By Quotes

Multiple License : NO

3. Clock Rate:

150 MHz

4. Logic Gate Count:


5. Technology:


6. Version: