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  • uIP: DDR4 SDRAM Controller Core
  • uIP ID: 2034072918
  • μIP Type: Digital μIP
  • HDL: Verilog
  • Warranty: YES
  • Simulation Tool: Model-sim
  • Tool Version:
  • Design Format: RTL and Netlist
  • Merge In Foundry: NO
    Designer Information
  • Member ID:2260941000400757
  • Designer Rating:
  • Feedback received:0
 

1. Introduction:

Double Data Rate 4 (DDR4) SDRAM Controller Core is designed for use in applications requiring high memory throughput, high clock rates and full programmability.

 

The core uses bank management modules to monitor the status of each SDRAM bank.  Banks are only opened or closed when necessary, minimizing access delays.  Up to 32 banks can be managed at one time. 

 

The core supports all new DDR4 features, including: 3DS device configurations, write CRC, data bus inversion (DBI), fine granu-larity refresh, additive latency, per-DRAM addressability, and temperature controlled refresh.


2. License Price:

By Quotes

Multiple License : NO


3. Clock Rate:

None


4. Logic Gate Count:

None


5. Technology:

None


6. Version:

1.0