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  • uIP: SPI slave in mode 1
  • uIP ID: 638192
  • μIP Type: Digital μIP
  • HDL: Verilog
  • Warranty: YES
  • Simulation Tool: Cadence NC-Verilog
  • Tool Version:
  • Design Format: Netlist
  • Merge In Foundry: NO
    Designer Information
  • Member ID:7520023000300058
  • Designer Rating:
  • Feedback received:0

1. Introduction:

The Serial Peripheral Interface (SPI) bus, established by Motorola, is a synchronous serial data link. It operates in master/slave and full duplex styles. That is, when a master device initiates a transaction and communicates with a certain slave device, they exchange data bit-by-bit. Furthermore, the single master communication is applied to the SPI bus. Thus, there is always a single master device (with one or more slave devices) on it.

The SPI bus contains 4 wires, with each named SCK, MOSI, MISO and SS_n respectively. You may also find alternative naming conventions elsewhere. The following table lists their functions and directions:

The typical SPI bus architecture is designed as follows:

When the SPI master device wants to communicate with a certain slave device, it asserts the SS_n line of that slave device, and then exchange data using the MOSI and MISO lines based on the toggling SCK line.

With clock polarity (CPOL) and clock phase (CPHA) set to different values, the SPI bus can operate in 4 modes. These modes are listed in the following table, where provide means that the communicating master and slave devices provide data on the MOSI and MISO lines respectively on the other hand, capture means that the communicating master and slave devices capture data on the MISO and MOSI lines respectively:


2. License Price:

1000 Points

Multiple License : YES

   - Discount for 2 ~ 5 license:5 %
   - Discount for 6 ~ 10 license:10 %
   - Discount for 11 ~ license:15 %

3. Clock Rate:

285 MHz

4. Logic Gate Count:

276 Gates

5. Technology:

130 nm

6. Version: