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  • uIP: AES Codec with 128-bit datapath
  • uIP ID: 1313541759
  • μIP Type: Digital μIP
  • HDL: Verilog
  • Warranty: YES
  • Simulation Tool: VCS & Verilog
  • Tool Version:
  • Design Format: RTL and Netlist
  • Merge In Foundry: NO
    Designer Information
  • Member ID:7180875000300386
  • Designer Rating:
  • Feedback received:0
 

1. Introduction:

The IP core implements the NIST FIPS-197 Advanced Encryption Standard and can be programmed to either encrypt or decrypt 128-bit blocks of  data using a 128-bit, 192-bit or 256-bit key. The IP has been carefully designed for high throughput applications with optimal logic resources utilization. The encryptor core accepts a 128-bit plaintext input word, and generates a corresponding 128-bit ciphertext output word using a supplied 128, 192, or 256-bit AES key. The decryptor core provides the reverse function, generating plaintext from supplied ciphertext, using the same AES key as was used for encryption. The hardware roundkey expansion logic has been designed as a discrete building block. This allows either to build a complete stand-alone AES solution, or to save logic resources by leaving the key generation process to the user. Alternatively, the roundkey expansion logic can be shared between multiple encryption/decryption cores for optimal silicon area resources utilization. The implementation is very low on latency, high speed with a simple interface for easy integration in SoC applications. 


2. License Price:

20000 Points

Multiple License : NO


3. Clock Rate:

260 MHz


4. Logic Gate Count:

22 K Gates


5. Technology:

180 nm


6. Version:

1.0