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  • uIP: CAN 2.0 & CAN FD Bus Controller Core
  • uIP ID: 1593297965
  • μIP Type: Digital μIP
  • HDL: VHDL
  • Warranty: YES
  • Simulation Tool: Synopsys VCS
  • Tool Version:
  • Design Format: RTL
  • Merge In Foundry: NO
    Designer Information
  • Member ID:1422368000800119
  • Designer Rating:
  • Feedback received:0
 

1. Introduction:

The CAN protocol uses a multi-master bus configuration for the transfer of frames be- tween nodes of the network and manages error handling with no burden on the host processor. The core enables the user to set up economic and reliable links between vari- ous components. It appears as a memory-mapped I/O device to the host processor, which accesses the CAN core to control the transmission or reception of frames.
The CAN core is easy to use and integrate, featuring programmable interrupts, data and baud rates; a configurable number of independently programmable acceptance filters; and a generic processor interface or optionally an AMBA APB, or AHB-Lite interface. It imple- ments a flexible buffering scheme, allowing fine-tuning of the core size to satisfy the requirements of each specific application

 


2. License Price:

By Quotes

Multiple License : NO


3. Clock Rate:

None


4. Logic Gate Count:

12 K Gates


5. Technology:

None


6. Version:

1