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  • uIP: Video Interlacer
  • uIP ID: 184834425
  • μIP Type: Digital μIP
  • HDL: Verilog
  • Warranty: YES
  • Simulation Tool: Model-sim
  • Tool Version:
  • Design Format: RTL
  • Merge In Foundry: NO
    Designer Information
  • Member ID:2001496000900412
  • Designer Rating:
  • Feedback received:0
 

1. Introduction:

The IP Core is a fully pipelined video interlacer solution that converts any progressive video format into it's interlaced equivalent. Each interlaced output field will have half the number of lines as an input frame.

The input and output interfaces are streaming interfaces that follow a simple valid-ready pipeline protocol. Input pixels and syncs are sampled on the rising edge of clk when P_VALID and  P_READY  are both high. Likewise, output pixels and syncs are sampled on the rising edge of clk when PO_VAL and PO_READY are high.

Note that if no flow control is required in the design and the output is guaranteed to accept pixels without stalling, then the signal  PO_READY may be tied high and the signal  P_READY may be ignored.

Application

  • Video solutions for flat panel displays, portable devices, video consoles, video format converters, set-top boxes, digital TV etc.
  • Conversion of all standard and custom video formats such as 1920x1080p to 1920x1080i, 720x480p to 720x480i etc.


2. License Price:

By Quotes

Multiple License : NO


3. Clock Rate:

500 MHz


4. Logic Gate Count:

None


5. Technology:

None


6. Version:

1.0