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  • uIP: Video Timing Generator
  • uIP ID: 1329929059
  • μIP Type: Digital μIP
  • HDL: Verilog
  • Warranty: YES
  • Simulation Tool: Synopsys VCS
  • Tool Version:
  • Design Format: RTL
  • Merge In Foundry: NO
    Designer Information
  • Member ID:4461480000700868
  • Designer Rating:
  • Feedback received:0

1. Introduction:

The IP Core is a fully configurable video timing generator with the ability to support any video resolution up to 216  x 216 pixels in size. The module is compatible with a wide range of video DACs, CODECs and transceivers and provides a flexible solution for displaying digital or analogue video on an external TV, monitor or flat panel display.  The module is capable of clock speeds in excess of 400 MHz on some FPGA platforms, making it ideal for the latest generation HD and UHD video solutions.

After resynchronizing the input pixels to the pixel-clock domain , the controller locks to the first frame (or field) of video. Once frame-lock is achieved, pixels are supplied on demand to the video timing control unit. This module generates the correct RGB video, sync and blanking information depending on the chosen timing parameters.


  • Legacy (SD) and analogue video applications
  • Digital TV and multimedia solutions
  • HD, UHD and SUHD next generation digital video


2. License Price:

By Quotes

Multiple License : NO

3. Clock Rate:

400 MHz

4. Logic Gate Count:


5. Technology:


6. Version: