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  • uIP: Dual-Channel 12-bit 80 MSPS ADC IP in UMC 65 nm
  • uIP ID: 1462254540
  • μIP Type: Analog μIP
  • HDL: Verilog Behavioral Model
  • Warranty: YES
  • Simulation Tool: Cadence NC-Verilog
  • Tool Version:
  • Design Format: GDS & Schematic
  • Merge In Foundry: NO
    Designer Information
  • Member ID:4422502000000537
  • Designer Rating:
  • Feedback received:0
 

1. Introduction:

ADC X is an ultra-compact and very low power analog-to-digital converter (ADC) IP. The 12-bit 80 MSPS Dual ADC includes an internal custom bandgap voltage reference. It is capable of supplying bias currents to other parallel ADCs. IP architecture is robust and can be ported to other

65 nm processes.The ADC uses fully differential pipeline architecture with custom low-disturbance digital correction technique which allows single supply bus for both digital and analog.


2. License Price:

By Quotes

Multiple License : NO


3. Trial Run Price:

By Quotes


4. Clock Rate:

0.8 MHz


5. Area:

450 μm^2


6. Technology:

65 nm


7. Version:

1.0