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  • uIP: PCI Express Gen4 PHY IP in 28nm HPC+
  • uIP ID: 917464071
  • μIP Type: Analog μIP
  • HDL: Verilog Behavioral Model
  • Warranty: YES
  • Simulation Tool: Cadence NC-Verilog
  • Tool Version:
  • Design Format: GDS & Schematic
  • Merge In Foundry: NO
    Designer Information
  • Member ID:7702538000400461
  • Designer Rating:
  • Feedback received:0

1. Introduction:

The Peripheral Component Interconnect Express (PCIe) x4 PHY is compliant with PCIe 4.0 Base Specification with support of PIPE v4.4 inter- face spec. Lower power consumption is achieved due to support of addition- al PLL control, reference clock control, and embedded power gating control. Also, since aforementioned low power mode setting is configurable, the PHY is widely applicable for various scenarios under different consideration of power consumption.

2. License Price:

By Quotes

Multiple License : NO

3. Trial Run Price:

By Quotes

4. Clock Rate:

25 MHz

5. Area:


6. Technology:

28 nm

7. Version: