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  • uIP: PLL 1600M UMC 28 nm logic and Mixed-Mode HPC process
  • uIP ID: 1458587876
  • μIP Type: Analog μIP
  • HDL: Verilog Behavioral Model
  • Warranty: YES
  • Simulation Tool: Cadence NC-Verilog
  • Tool Version:
  • Design Format: GDS
  • Merge In Foundry: NO
    Designer Information
  • Member ID:8972661000700018
  • Designer Rating:
  • Feedback received:0
 

1. Introduction:

A Phase-Locked Loop (PLL) with an operating frequency ranging from 200 MHz to 1600 MHz.
This PLL is designed with the UMC 28 nm logic and Mixed-Mode HPC process.
It can be integrated into a chip to generate a high-speed clock.
The embedded divide-by-4 loop divider allows users to boost the output frequency of up to 1600 MHz.


2. License Price:

By Quotes

Multiple License : NO


3. Trial Run Price:

By Quotes


4. Clock Rate:

1.6 GHz


5. Area:

270 μm^2


6. Technology:

28 nm


7. Version:

1