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  • uIP: PLL 3000M UMC 28 nm logic and Mixed-Mode HPC process
  • uIP ID: 582169968
  • μIP Type: Analog μIP
  • HDL: Verilog Behavioral Model
  • Warranty: YES
  • Simulation Tool: Cadence NC-Verilog
  • Tool Version:
  • Design Format: LEF
  • Merge In Foundry: YES
    Designer Information
  • Member ID:8972661000700018
  • Designer Rating:
  • Feedback received:0

1. Introduction:

It generates a stable high-speed clock from an external slower reference clock signal. It integrates a Voltage-Controlled Oscillator (VCO), a Phase-Frequency Detector (PFD), a Low-Pass Filter (LPF), a 9-bit programmable loop divider, a 2-bit programmable pre-divider and associated support circuitry. This PLL is designed by using the UMC 28 nm logic and Mixed-Mode HPC process, and it supports an operating voltage ranging from 0.81 V to 0.99 V with an operating junction temperature ranging between -40 °C and 125 °C. It accepts FREF frequency ranging from 6 MHz to 27 MHz and generates the output frequency up to 3000 MHz.

2. License Price:

By Quotes

Multiple License : NO

3. Trial Run Price:

By Quotes

4. Clock Rate:

27 MHz

5. Area:

92.4 K μm^2

6. Technology:

28 nm

7. Version: