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JPEG-MT-V By Quotes None None None  
This JPEG compression IP core supports the Baseline Sequential DCT and the Ex- tended Sequential DCT modes of the ISO/IEC 10918-1 standard. It implements a scalable, ultra-high-performance, ASIC or FPGA, hardware JPEG encoder that can compress high pixel rate video using significantly fewer silicon resources and less pow- er than encoders for video compression standards such as HEVC/H,265, DSC, AVC/H.264, or JPEG200. The JPEG-MT-V Encoder produces compressed JPEG images and the video payload for Motion-JPEG container formats. It accepts images with up to 12-bit color samples and up to four color components, in all widely-used color subsampling formats. Depending on its configuration, the encoder processes from two to 32 color samples per clock cycle, enabling it to compress UHD (4K/8K) video and/or very high frame vid- eo. Once programmed, the easy-to-use encoder requires no assistance from a host pro- cessor to compress an arbitrary number of frames. SoC integration is straightforward thanks to standardized AMBA® interfaces: AXI Streaming for pixel and compressed da- ta, and a 32-bit APB slave interface for registers access. Users can optionally insert timestamps or other metadata in the compressed stream using a dedicated AXI Stream- ing interface.   Introduction
JPEG-ST-V By Quotes None None None  
This JPEG decompression IP core supports the Baseline Sequential DCT and Extend- ed Sequential DCT modes of the ISO/IEC 10918-1 standard. It implements a scalable, ultra-high-performance, ASIC or FPGA, hardware JPEG decoder that handles extreme- ly high pixel rates. The JPEG-ST-V Decoder decompresses JPEG images and the video payload for Mo- tion-JPEG container formats. It accepts compressed streams of images with 8- or 12-bit color samples and up to four color components, in all widely-used color subsampling formats. Depending on its configuration, the decoder processes from two to 32 color samples per clock cycle. Its high throughput capabilities are best exploited when decompressing streams produced by the JPEG-MT-V Encoder Core. This Encoder-Decoder pair pro- vide an extremely cost effective solution for streaming or archiving UHD (4K/8K) video, or very high frame rates at lower resolutions. Once programmed, the easy-to-use decoder operates on a standalone basis, parsing marker segments and decompressing coded data with no assistance from a host pro- cessor. The decoder reports the image format (i.e., resolution, subsampling format, and color sample-depth) to the system, so that the decoded images are properly further processed and/or displayed. Introduction
ASRC-Pro : 24-bit -130dB THD+N Multi-Channel Audio Sample Rate Converter By Quotes None 192 KHz 45 nm  
The ASRC-pro is part of multi-channel Asynchronous Audio Sample Rate Converters (ASRC). This core can be used to interface digital audio equipments operating at different sample rates. It has been designed for systems requiring very high quality in terms of low harmonic distortion and noise, tolerance and rejection of input jitter. The ASRC-pro can perform common sample rate conversions with less than -130 dB of Total Harmonic Distortion plus Noise (THD+N) and has a Dynamic range of 131 dB, supporting input data processing of up to 24-bit resolution. The ASRC series are implemented to support several key industry interfaces: TDM parallel, TDM serial, Parallel, I2S, SPDIF-AES3. We offers a broad range of asynchronous sample rate converters targeted for variety of audio applications. Application: Set-top boxes, professional and hi-fi audio Home Theater Systems Automotive Audio Systems Digital Audio Effects Processors Digital Audio Broadcast Equipment Introduction
ASRC-Lite : 16-bit -90dB THD+N Multi-Channel Audio Sample Rate Converter By Quotes None 192 KHz 45 nm  
The ASRC-lite  is part of multi-channel asynchronous Audio Sample Rate Converter (ASRC). This core can be used to interface digital audio equipments operating at different sample rates. It has been designed for systems that require a low-cost solution, maintaining low harmonic distortion and noise, and a high tolerance and rejection of input jitter. The ASRC-lite can perform common sample rate conversions with less than -90 dB of Total Harmonic Distortion plus Noise (THD+N) and has a Dynamic range of 92 dB, supporting input data of 16-bit resolution. The ASRC series are implemented to support several key industry interfaces: TDM parallel, TDM serial, Parallel, I2S, SPDIF-AES3. We offers a broad range of asynchronous sample rate converters targeted for variety of audio applications   Application : Set-top boxes, professional and hi-fi audio Home Theater Systems Automotive Audio Systems Digital Audio Effects Processors Digital Audio Broadcast Equipment Introduction
The TDM-Rx-Pro is part of proven audio interface cores featuring a configurable multi-channel audio By Quotes None 192 KHz 65 nm  
The TDM-Rx-Pro  is part of proven audio interface cores featuring a configurable multi-channel audio interface designed to input serial (TDM) digital audio streams from various manufacturers. The TDM-Rx-Pro front-end also supports the well known stereo formats: Philips I2S, Left-Justified or Right-Justified. The TDM-Rx-Pro backend is supplied with a choice of AMBA®, CoreConnect™ or a flexible parallel interface. Introduction
H.264 Encoder IP Core By Quotes None 150 MHz None  
This H.264 Encoder IP core has been developed to be the highest throughput standards compliant hardware H.264 video compressor.  The IP offers two encoder variants to meet the different targets of features.   The IP include 2 mode. H264E-I: H.264 encoder compliant with CAVLC 4:4:4 Intra Profile (all frames are keyframes)​         The IP core is smaller but yields less compression. It does not require external memory. H264E-P: H.264 encoder compliant with High 4:4:4 Predictive Profile:   The IP core is larger but offers a significantly better compression. Both share the same outstanding processing speed of more than 5.2 pixels encoded per cycle. The data interfaces in the H.264 Encoder IP Core use the AXI industry standard.  The Master I/O data interfaces use an AXI3 bus, forward compatible with AXI4 interconnects. Introduction
ITU-R BT.656 video encoder By Quotes None 200 MHz None  
ITU-R_BT is a digital video encoder with integrated colour-space converter.   The encoder accepts 24-bit RGB pixels from sequential odd and even fields.   These pixels are then mapped to the YCbCr colour-space and formatted correctly into a BT output stream. The output of the encoder generates an industry standard ITU-R BT.656 format video stream together with a video_val signal that is asserted with the first valid byte of the output stream.   Applications BT.656 output video generation PAL & NTSC SDTV video format conversion   Introduction
Text Overlay Module By Quotes None 200 MHz None  
The IP Core is a highly versatile On Screen Display (OSD) module that allows text and bitmap graphics to be inserted over RGB video.   The module supports a wide range of text effects and the programming interface is very simple.  Text is written to a 64x32 character buffer which is mapped (via a bitmap ROM) directly to the display. The characters in the buffer are displayed in a 'TEXT BOX' which may be positioned anywhere in the video display area. Bitmaps for each character are stored in a ROM which may be modified to support different font styles or bitmap graphics. Pixels and syncs flow in and out of the overlay module in accordance with the valid-ready pipeline protocol.  Application Window movement in the same manner as a 2D 'BitBlt' Terminal and Console windows Low cost text and graphics applications Digital TV and home-media solutions Introduction
2D Graphics Overlay By Quotes None 200 MHz None  
This is a highly versatile on-screen display that allows high-quality anti-aliased bitmap graphics to be inserted over RGB video. The module supports a wide range of graphics effects and the programming interface is very simple to use. The bitmap overlay is partitioned into an array of tiles which are addressed by means of an 8-bit value stored in a 64x64 tile buffer. There are four tile sizes available - either 8x8, 16x16, 32x32 or 64x64. The tiles in the buffer are displayed in a graphics window which may be positioned anywhere within the display area. Bitmaps for each tile are stored in a user-defined ROM which can contain up to  256  different bitmaps stored over three bit-planes. Depending on the chosen graphics mode, the 3-bits per pixel may be used to select one colour from a palette of eight, eight levels of alpha transparency or seven colours on a transparent background. Pixels and syncs flow in and out of the overlay module in accordance with the valid-ready pipeline protocol. Application Animated 2D graphics including hardware sprites, mouse pointers, cursors , parallax scrolling, moving banners etc. Interactive guides, menus, tables, lists etc. Digital TV and home-media solutions Professional and functional 2D graphic displays and video overlays   Introduction
Motion-adaptive Video Deinterlacer By Quotes None 200 MHz None  
The IP Core is a studio quality 24-bit RGB video deinterlacer capable of generating progressive output video at any resolution up to 216 x 216  pixels. The design is fully programmable and supports any desired interlaced video format. The design allows for three possible deinterlacing schemes. These are: weave, bilinear interpolation or motion-adaptive interpolation. The weave approach applies no filtering and may be useful to obtain a 'raw' interlaced format for subsequent processing. The other two methods are classed as 'inter-field' interpolation methods as spatial filtering is performed between both odd and even fields to achieve a clean and progressive output. The relative merits and disadvantages of each scheme are discussed further into the document. The deinterlacer core features a fully integrated video frame buffer. This buffer is completely 'elastic' and will dynamically skip and/or repeat frames depending on the input and output frame rates. All frame buffer management is handled internally with the provision of a simple memory interface for storing odd and even fields off-chip. The memory interface is 128-bits wide and is completely  generic. All memory transfers are sequential bursts of N x 128-bit words and may be adapted for connection to a variety of memory types such as SDRAM, DDR2 or DDR3. Application Digital TV set-top boxes. Industrial imaging. Automotive, home and personal media solutions Conversion of 'legacy' SDTV formats to HDTV video formats Generating progressive RGB video via inexpensive PAL/NTSC decoder chips Studio-quality video de-interlacing Introduction
μIP Price Logic Gate Count Clock Rate Technology   Ratings

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