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Video Frame Buffer By Quotes None 300 MHz None  
VID_FB is a high-speed multi-format video frame buffer that asynchronously samples an input video stream and buffers it in an   external   memory. Output   pixels   are   read   out   of   the   buffer   and synchronised to the system clock domain.  The VID_FB will automatically adapt to different input and output frame rates. If the input frame rate is too high, then the VID_FB will cleanly drop or 'skip' an input frame.  Likewise, if the output frame rate is higher than the input frame rate, then frames will be repeated 3 .   The result is a system that seamlessly adapts to the different frame rates at the input and output of the VID_FB.   Applications Buffering video frames in external memory Real-time digital video applications Genlocking of multiple video sources   Introduction
ITU-R BT.656 video encoder By Quotes None 200 MHz None  
ITU-R_BT is a digital video encoder with integrated colour-space converter.   The encoder accepts 24-bit RGB pixels from sequential odd and even fields.   These pixels are then mapped to the YCbCr colour-space and formatted correctly into a BT output stream. The output of the encoder generates an industry standard ITU-R BT.656 format video stream together with a video_val signal that is asserted with the first valid byte of the output stream.   Applications BT.656 output video generation PAL & NTSC SDTV video format conversion   Introduction
ITU-R BT.656 video decoder By Quotes None 300 MHz None  
DEC_BT656 is a digital video decoder with integrated colour-space converter.  It's function is to extract the valid pixels from a BT.656 video stream and convert them to 24-bit RGB for subsequent processing. Pixels   are   extracted   from   the   BT.656   input   stream   and   converted   to RGB888 format.    Application  BT.656 input video capture and processing PAL & NTSC SDTV interlaced format conversion Introduction
Color-space Converter By Quotes None 400 MHz None  
This  IP  is a fully pipelined color-space converter that converts pixels between the RGB and YCbCr color spaces.  In total, the IP Core package contains two distinct modules – one module that converts   from   24-bit   RGB   to   30-bit   4:4:4   YCbCr   and   the   other   that performs the reciprocal operation from 4:4:4 YCbCr to RGB.   Application Digital video and image processing  Introduction
H.264 Encoder IP Core By Quotes None 150 MHz None  
This H.264 Encoder IP core has been developed to be the highest throughput standards compliant hardware H.264 video compressor.  The IP offers two encoder variants to meet the different targets of features.   The IP include 2 mode. H264E-I: H.264 encoder compliant with CAVLC 4:4:4 Intra Profile (all frames are keyframes)​         The IP core is smaller but yields less compression. It does not require external memory. H264E-P: H.264 encoder compliant with High 4:4:4 Predictive Profile:   The IP core is larger but offers a significantly better compression. Both share the same outstanding processing speed of more than 5.2 pixels encoded per cycle. The data interfaces in the H.264 Encoder IP Core use the AXI industry standard.  The Master I/O data interfaces use an AXI3 bus, forward compatible with AXI4 interconnects. Introduction
JPEG Encoder By Quotes None 250 MHz 130 nm  
This IP core has been developed to be a complete standards compliant JPEG / MJPEG Hardware Compressor / Encoder. The data interfaces in the JPEG Encoder IP Core (JPEGE) use the AXI industry standard. The Master I/O data interfaces use an AXI3 bus, forward compatible with AXI4 interconnects. In order to let you assess the properties of the on-the-fly selectable quality setting, please use the slider below the image in order to see the final compressed image and compression ratio. The JPEG Encoder IP Core has a real throughput of two compressed pixels every three clock cycles at any compression ratio for a chroma subsampling of 4:2:0. To calculate the throughput for your platform. Introduction
JPEG Decoder By Quotes None 250 MHz 130 nm  
This JPEG Decoder IP core has been developed to be a complete standards compliant JPEG / MJPEG Hardware Decompressor / Decoder. When decoding JPEG images, pixel throughput can not be fixed for compressed JPEGs of arbitrary quality, as it depends on the compression ratio (bits needed to encode one pixel). To circumvent this limitation JPEG Decoder IP features a dual pixel component pipeline, allowing for greater decoding speeds.   Introduction
Digital Video Scaler By Quotes None 250 MHz None  
The IP Core is a studio  quality video scaler capable  of generating interpolated output images from 16 x 16 up to  216  x 216  pixels in resolution.   The architecture permits seamless scaling (either up or down) depending on the chosen scale factor.  Internally, the scaler uses a 24-bit accumulator and a bank of polyphase FIR filters with 16 phases or interpolation points.  All filter coefficients are programmable, allowing the user to define a wide range of filter characteristics. Pixels flow in and out of the video scaler in accordance with the valid-ready pipeline protocol.  Pixels are transferred into the scaler on a rising clock-edge when pixin_val  is high and pixin_rdy is high.  As such, the pipeline protocol allows both input and output interfaces to be stalled independently. The scaler is partitioned into a horizontal scaling module in series with a vertical scaling module . Application Support for the latest generation video formats with resolutions of 4K and above Video scaling for flat panel displays, portable devices, video consoles, video format converters, set-top boxes, digital TV etc. Conversion of all standard and custom video resolutions such as HD720P to HD1080P, XGA to VGA etc.   Introduction
Bilinear Video Scaling Engine By Quotes None 250 MHz None  
This IP is a very high quality video scaler capable of generating interpolated output images from 16x16 up to 216  x 216  pixels in resolution. The architecture permits seamless scaling (either up or down) depending on the chosen scale factor. Internally, the scaler uses a 24-bit accumulator and a bank of polyphase FIR filters with 16 phases or interpolation points.  All filter coefficients are programmable, allowing the user to define a wide range of filter characteristics. Pixels flow in and out of the scaling engine in accordance with the valid-ready pipeline protocol.As such, the pipeline protocol allows both input and output interfaces to be stalled independently. The scaler is partitioned into a horizontal scaling section in series with avertical scaling section. Application Conversion of popular video formats to any other resolution such as VGA to XGA, SVGA to HD1080 etc. Picture in Picture (PiP) applications High quality 24-bit RGB/YCbCr video scaling     Introduction
Text Overlay Module By Quotes None 200 MHz None  
The IP Core is a highly versatile On Screen Display (OSD) module that allows text and bitmap graphics to be inserted over RGB video.   The module supports a wide range of text effects and the programming interface is very simple.  Text is written to a 64x32 character buffer which is mapped (via a bitmap ROM) directly to the display. The characters in the buffer are displayed in a 'TEXT BOX' which may be positioned anywhere in the video display area. Bitmaps for each character are stored in a ROM which may be modified to support different font styles or bitmap graphics. Pixels and syncs flow in and out of the overlay module in accordance with the valid-ready pipeline protocol.  Application Window movement in the same manner as a 2D 'BitBlt' Terminal and Console windows Low cost text and graphics applications Digital TV and home-media solutions Introduction
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