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12-Bit 800KSPS Low Power SAR-ADC By Quotes None 25 MHz 180 nm  
The SAR-ADC is a low power ADC that is implemented in Successive Approximation architecture. It can provide 12-bit resolution capability with only 3V supply voltage. It accepts an analog input range from 0 to VCC   and digitizes the input at a maximum sampling frequency rate of 800KHz at 5V supply voltage. This ADC also includes MUX design to select 0 of 7 analog inputs. The power dissipation is less than 5mW with 5V power supply. This SAR-ADC is implemented in SMIC 0.18μm generic CMOS technology. Introduction
8-Bit 7 GSPS SAR ADC By Quotes 300.000 K μm^2 7 GHz 16 nm  
This IP is compact and low power 8-bit Time interleaved SAR analog-to-digital converter silicon IP.This ADC uses fully differential SAR architecture optimized for low power and small silicon area.     APPLICATIONS Serdes Receiver Coherent Transceivers Data acquisition Introduction
32 bits RISC Microcontroller By Quotes 33.000 K Gates 100 MHz 180 nm  
The CPU Core is a 32-bit microprocessor. It has a 32-bit data path, a 32-bit register bank, and 32-bit memory interfaces. The processor has a Harvard architecture, which means that it has a separate instruction bus and data bus. This allows instructions and data accesses to take place at the same time, and as a result of this, the performance of the processor increases because data accesses do not affect the instruction pipeline.However, the instruction and data buses share the same memory space (a unified memory system). In other words, you cannot get 8 GB of memory space just because you have separate bus interfaces. Applications Wearables IoT Motor Control Appliances Connectivity Smart home/building/enterprice/planet Introduction
8051 Core By Quotes None 20 MHz None  
The 8051 has gained great popularity since its introduction and is estimated it is  used in a large percentage of all embedded system products.  The  basic  form  of  8051  core  includes  several  on-chip  peripherals,  like  timers  and  counters, additionally there are 128 bytes of on-chip data memory and up to 4K bytes of  on-chip program memory. Introduction
UART Serial Interface Controller By Quotes None 300 MHz None  
UART compatible Serial Interface Controller with receive and transmit FIFOs and support for all standard bit rates from 9600 to 921600 baud.    Applications UART Communications RS232, RS422, RS485 etc. Micro-controller interfacing Introduction
I2C Master Serial Interface Controller By Quotes None 300 MHz None  
Master serial controller compatible with the popular Philips® I2C standard. Features a simple command interface and permits multiple I2C slaves to be controlled directly from  ASIC device. Supports standard (100 kbits/s), fast (400 kbits/s) and custom data rates well above 4 Mbits/s. Setup and hold-times on the SDA pin are fully configurable.    Applications Inter-chip board-level communications Standard 2-wire comms between a wide range of peripherals, MCUs and COTs ICs   Introduction
I2C Slave Serial Interface Controller By Quotes None 300 MHz None  
Slave serial controller compatible with the popular Philips® I2C standard. Permits an I2C Master to communicate with your ASIC device via a set of user-defined config and status registers. Supports standard (100 kbits/s), fast (400 kbits/s) and custom rates in excess of 4 Mbits/s.    Applications I2C slave communication via your ASIC Inter-chip board-level communications Introduction
8-bit / 16-bit Flash memory controller By Quotes None 200 MHz None  
FLASH memory controller ideal for interfacing to a wide range of parallel FLASH memory components . Features a fully synchronous command interface and a set of configurable timing parameters for compatibility with different devices.  Applications Any application where non-volatile storage is required Offline storage of parameters and data via your Chip     Introduction
DDR4 SDRAM Controller Core By Quotes None None None  
Double Data Rate 4 (DDR4) SDRAM Controller Core is designed for use in applications requiring high memory throughput, high clock rates and full programmability.   The core uses bank management modules to monitor the status of each SDRAM bank.  Banks are only opened or closed when necessary, minimizing access delays.  Up to 32 banks can be managed at one time.    The core supports all new DDR4 features, including: 3DS device configurations, write CRC, data bus inversion (DBI), fine granu-larity refresh, additive latency, per-DRAM addressability, and temperature controlled refresh. Introduction
Automotive Electronics Platform By Quotes None None None  
This Platform can decrease timing for develop. Single Chip Solution Integrated Pressure Sensor Integrated Acceleration Sensor Integrated Temperature Sensor 32-bit RISC CPU PWM RF Transmitter (300-450 Mhz) LF Receiver Easy Integrated Customer’s Logic ​ Application Tire Pressure Monitoring System Automotive electronics Introduction
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