TW / Global Website







IP Mart




Mart > IP Mart

    
AES Codec with 128-bit datapath 20000 Points 22.000 K Gates 260 MHz 180 nm 2016/02/15
The IP core implements the NIST FIPS-197 Advanced Encryption Standard and can be programmed to either encrypt or decrypt 128-bit blocks of  data using a 128-bit, 192-bit or 256-bit key. The IP has been carefully designed for high throughput applications with optimal logic resources utilization. The encryptor core accepts a 128-bit plaintext input word, and generates a corresponding 128-bit ciphertext output word using a supplied 128, 192, or 256-bit AES key. The decryptor core provides the reverse function, generating plaintext from supplied ciphertext, using the same AES key as was used for encryption. The hardware roundkey expansion logic has been designed as a discrete building block. This allows either to build a complete stand-alone AES solution, or to save logic resources by leaving the key generation process to the user. Alternatively, the roundkey expansion logic can be shared between multiple encryption/decryption cores for optimal silicon area resources utilization. The implementation is very low on latency, high speed with a simple interface for easy integration in SoC applications.  Introduction
AES Codec with 8-bit datapath 20000 Points 1.300 K Gates 515 MHz 180 nm 2016/01/20
The IP core implements the NIST FIPS-197 Advanced Encryption Standard and can be programmed to either encrypt or decrypt 128-bit blocks of data using a 128-bit, 192-bit or 256-bit key. The IP has been carefully designed to require minimum logic resources rendering it an ideal solution for low power applications. This has been achieved by using an 8-bit data path size which means that 16 clock cycles are required to load/unload the 128-bit plaintext/ciphertext block. The encryptor receives the 128-bit plaintext block in 8-bit input symbols and generates the corresponding 128-bit ciphertext block in 8-bit output symbols using a supplied 128, 192, or 256-bit AES key. The pre-computed key values are read from an internal round key RAM. A key expander module is provided as an optional module to allow automatic generation and loading of the round key RAM. The decryptor implements the reverse function, generating plaintext from supplied ciphertext, using the same AES key as was used for encryption. The implementation is very low on latency, high speed with a simple interface for easy integration in SoC applications.  Introduction
Configurable Reed Solomon Encoder 30000 Points 2.500 K Gates 250 MHz 180 nm 2015/12/30
Our IP core implements the Reed Solomon encoding algorithm and is parameterized in terms of bits per symbol, maximum codeword length and maximum number of parity symbols. It  also  supports  varying  on  the  fly   shortened  codes.  Therefore  any desirable code-rate can be easily achieved rendering the decoder ideal for fully adaptive FEC applications. ntRSE core supports continuous or burst  decoding.  The  implementation  is  very  low  latency,  high  speed with a simple interface for easy integration in SoC applications. Introduction
[110nm]10-bit 80 MSPS ADC IP 30000 Points 210.000 K μm^2 80 MHz 110 nm 2015/11/23
UIP_ADC10_80M_183288 is an ultra-compact and very low power analog-to-digital converter (ADC) silicon IP. The 10-bit 80 MSPS ADC includes an internal custom bandgap voltage reference. It is capable of supplying bias currents to other parallel ADCs.   The ADC uses fully differential pipeline architecture with custom low-disturbance digital correction technique which allows single supply bus for both digital and analog. The ADC is designed for high dynamic performance for input frequencies up to Nyquist. This makes the IP perfectly suitable for video, imaging and communication appliances.   The IP is available in different metal options as well as deep N-well (DNW) option for SoC with high level of substrate noise. It consumes only 24mW at 80 MSPS operation and requires silicon area of 0.21 mm2. The IP does not require any external decoupling and is ideal for integration in mixed-signal systems. The output data of ADC is available in 2’s complement format.   UIP_ADC10_80M_183288 can be used in the following applications:   ‧Digital imaging ‧TV/Video ‧Wireless LAN ‧Rx communication channel Introduction
[110nm] 10-bit 165 MSPS ADC IP 30000 Points 210.000 K μm^2 165 MHz 110 nm 2015/11/21
UIP_ADC10_165M_213779 is an ultra-compact and very low power analog-to-digital converter (ADC) silicon IP. The 10-bit 165 MSPS ADC includes an internal custom bandgap voltage reference. It is capable of supplying bias currents to other parallel ADCs.   The ADC uses fully differential pipeline architecture with custom low-disturbance digital correction technique which allows single supply bus for both digital and analog. The ADC is designed for high dynamic performance for input frequencies up to Nyquist. This makes the IP perfectly suitable for video, imaging and communication appliances.   The IP is available in different metal options as well as deep N-well (DNW) option for SoC with high level of substrate noise. It consumes only 48mW at 165 MSPS operation and requires silicon area of 0.21 mm2. The IP does not require any external decoupling and is ideal for integration in mixed-signal systems. The output data of ADC is available in 2’s complement format.   UIP_ADC10_165M_213779 can be used in the following applications:   ‧Digital imaging ‧TV/Video ‧Wireless LAN ‧Rx communication channel ‧IOT Introduction
10-bit 80 MSPS ADC IP in 130 nm 30000 Points 210.000 K μm^2 80 MHz 130 nm 2015/11/19
UIP_ADC10_80M_156287 is an ultra-compact and very low power analog-to-digital converter (ADC) silicon IP. The 10-bit 80 MSPS ADC includes an internal custom bandgap voltage reference. It is capable of supplying bias currents to other parallel ADCs.   The ADC uses fully differential pipeline architecture with custom low-disturbance digital correction technique which allows single supply bus for both digital and analog. The ADC is designed for high dynamic performance for input frequencies up to Nyquist. This makes the IP perfectly suitable for video, imaging and communication appliances.   The IP is available in different metal options as well as deep N-well (DNW) option for SoC with high level of substrate noise. It consumes only 24mW at 80 MSPS operation and requires silicon area of 0.21 mm2. The IP does not require any external decoupling and is ideal for integration in mixed-signal systems. The output data of ADC is available in 2’s complement format.   UIP_ADC10_80M_156287 can be used in the following applications:   ‧Digital imaging ‧TV/Video ‧Wireless LAN ‧Rx communication channel Introduction
10-bit 165 MSPS ADC IP in 130 nm 30000 Points 210.000 K μm^2 165 MHz 130 nm 2015/11/17
UIP_ADC10_165M_166413 is an ultra-compact and very low power analog-to-digital converter (ADC) silicon IP. The 10-bit 165 MSPS ADC includes an internal custom bandgap voltage reference. It is capable of supplying bias currents to other parallel ADCs.   The ADC uses fully differential pipeline architecture with custom low-disturbance digital correction technique which allows single supply bus for both digital and analog. The ADC is designed for high dynamic performance for input frequencies up to Nyquist. This makes the IP perfectly suitable for video, imaging and communication appliances.   The IP is available in different metal options as well as deep N-well (DNW) option for SoC with high level of substrate noise. It consumes only 48mW at 165 MSPS operation and requires silicon area of 0.21 mm2. The IP does not require any external decoupling and is ideal for integration in mixed-signal systems. The output data of ADC is available in 2’s complement format.   UIP_ADC10_165M_166413 can be used in the following applications:   ‧Digital imaging ‧TV/Video ‧Wireless LAN ‧Rx communication channel ‧IOT Introduction
WiFi Frequency Synthesizer IP In 2.4GHz Band 100000 Points 200.000 K μm^2 3.2 GHz 55 nm 2015/10/12
The frequency  synthesizer  uses  a  single  1.25V  power supply.  Good  noise  immunity  allows  this  IP  to  be integrated  in  a  noisy  SOC environment.  The  synthesizer  operates  at  1.5X  WiFi  2.4GHz  band  for  wireless application.  Introduction
10-bit 300 MSPS Video DAC IP in 90 nm 30000 Points 76.000 K μm^2 300 MHz 90 nm 2015/06/13
The  UIP_DAC10-300M_205370  is  a  10-bit  DAC designed  in  low  power  TSMC  90  nm  logic process. It consists of a current steering DAC. The DAC uses a fully differential architecture. The  input  data  of  the  DAC  is  in  1.2V,  in unsigned format.   A 3.3V  supply  is used for  the analog  portion of  the  IP.  This  high  performance  DAC  is designed  for  CVBS  standard  or  RGB  Video signal  bandwidth.  The  IP  consumes  only  41 mA  at  300  MSPS  operation  and  utilizes  a silicon area of only 0.076 mm2. The IP does not  require  any  external  decoupling  and  is ideal for integration in mixed-signal systems.   The  DAC  output  current  is  6-bit programmable.  The  IP  architecture  is  robust and can be ported to other 90 nm processes.   APPLICATIONS Composite Video (CVBS) HDTV RGB Video ​ DAC Output Model Introduction
10-bit 165 MSPS ADC IP in 28 nm 50000 Points 70.000 K μm^2 165 MHz 28 nm 2015/05/27
UIP_ADC10_165M_809744 is an ultra-compact and very low power analog-to-digital converter (ADC) silicon IP. The 10-bit 165 MSPS ADC includes an internal custom bandgap voltage reference. It is capable of supplying bias currents to other parallel ADCs.   The ADC uses fully differential pipeline architecture with custom low-disturbance digital correction technique which allows single supply bus for both digital and analog. The ADC is designed for high dynamic performance for input frequencies up to Nyquist. This makes the IP perfectly suitable for video, imaging and communication appliances.   The IP is available in different metal options as well as deep N-well (DNW) option for SoC with high level of substrate noise. It consumes only 12mW at 165 MSPS operation and requires silicon area of 0.07 mm2. The IP does not require any external decoupling and is ideal for integration in mixed-signal systems. The output data of ADC is available in 2’s complement format.   UIP_ADC10_165M_809744 can be used in the following applications:   ‧Digital imaging ‧TV/Video ‧Wireless LAN ‧Rx communication channel ‧IOT Introduction
μIP Price Logic Gate Count Clock Rate Technology Released Date Ratings

 2  3  4  5  6  7  8  9  10  11