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Dual-Channel 12-bit 80 MSPS ADC IP in UMC 65 nm By Quotes 450.000 μm^2 0.8 MHz 65 nm  
ADC X is an ultra-compact and very low power analog-to-digital converter (ADC) IP. The 12-bit 80 MSPS Dual ADC includes an internal custom bandgap voltage reference. It is capable of supplying bias currents to other parallel ADCs. IP architecture is robust and can be ported to other 65 nm processes.The ADC uses fully differential pipeline architecture with custom low-disturbance digital correction technique which allows single supply bus for both digital and analog. Introduction
12-Bit 50 MSPS ADC in IBM 180 SOI By Quotes 280.000 μm^2 50 MHz 180 nm  
MICIP_ADC12 is compact and low power 12-bit analog-to-digital converter silicon IP. This ADC uses 1.5b/stage pipelined architecture optimized for low power and small area. Introduction
High Stable Timers IP By Quotes None 0.8 MHz None  
Timers are used for scheduling the different activities within the system. Timers generates interrupt in system and Operating system(OS) Schedules different Timers and maps them to different Interrupt Service Routine (ISR) to start on different interrupts. It can happen before starting a activity or application, OS configures a timers and give control to application to operate. On Interrupt trigger a interrupt, ISR kicks in and passes control back to OS. A Miss Function on this block can make system to mis-behave a lot. These section explains issues with normal timers and benefits of this high stable timers over conventional timers. -The Problem with Current Technology  Timers carry large counters, Registers, clocks pre-scalers and synchronizations and all these are built by Simple Components which do not have any stability.  If the SOC is exposed to different hazards like radiations, sparks or other events. These logics can be corrupted within counters and registers carrying configuration. This may result in corruption in stored configurations or counters or data or control passing by and can make interrupts to be generated fast or slower rate or even stopped. If system gets faster interrupt, then expected will make control to passed back to Operating system(OS) from the application or much before the application actually able to complete the task. This make system to not able to perform the required task. if interrupts generation is slowed down, will keep the OS waiting much longer to get control and application work is finished long back. This can make system to slow down or Hang. -The Solution High Stable Timers from GreenIPCore can sustain across all system un-stability and misbehavior problems. This Timers is strengthening system against any kind of dirty Electromagnetic noise and capable of protecting the System operation without disruption. The Timers is constructed with high stable components. The High Stable Timers shown above will not fail due to any hazardous event.   Introduction
10/100/1000 Gigabit Ethernet Transceiver By Quotes None None None  
The MIPG PHY is part of the A family of devices - which includes the MIPG PHY-031, MIPG PHY-033, and the MIPG PHY. It is A company’ 4th generation, single port 10/100/1000 Mbps Tri-speed Ethernet PHY. It supports RGMII interface to the MAC.™ The MIPG PHY provides a low power, low BOM (Bill of Materials) cost solution for comprehensive applications including consumer, enterprise, carrier and home networks such as PC, HDTV, Gaming machines, Blue-ray players, IPTV STB, Mdia Players, IP Cameras, NAS, Printers, Digital Photo Frames, MoCA/Homeplug (Powerline)/EoC/ adapters and Home Router & Gateways, etc. Introduction
JPEG-ST-V By Quotes None None None  
This JPEG decompression IP core supports the Baseline Sequential DCT and Extend- ed Sequential DCT modes of the ISO/IEC 10918-1 standard. It implements a scalable, ultra-high-performance, ASIC or FPGA, hardware JPEG decoder that handles extreme- ly high pixel rates. The JPEG-ST-V Decoder decompresses JPEG images and the video payload for Mo- tion-JPEG container formats. It accepts compressed streams of images with 8- or 12-bit color samples and up to four color components, in all widely-used color subsampling formats. Depending on its configuration, the decoder processes from two to 32 color samples per clock cycle. Its high throughput capabilities are best exploited when decompressing streams produced by the JPEG-MT-V Encoder Core. This Encoder-Decoder pair pro- vide an extremely cost effective solution for streaming or archiving UHD (4K/8K) video, or very high frame rates at lower resolutions. Once programmed, the easy-to-use decoder operates on a standalone basis, parsing marker segments and decompressing coded data with no assistance from a host pro- cessor. The decoder reports the image format (i.e., resolution, subsampling format, and color sample-depth) to the system, so that the decoded images are properly further processed and/or displayed. Introduction
JPEG-MT-V By Quotes None None None  
This JPEG compression IP core supports the Baseline Sequential DCT and the Ex- tended Sequential DCT modes of the ISO/IEC 10918-1 standard. It implements a scalable, ultra-high-performance, ASIC or FPGA, hardware JPEG encoder that can compress high pixel rate video using significantly fewer silicon resources and less pow- er than encoders for video compression standards such as HEVC/H,265, DSC, AVC/H.264, or JPEG200. The JPEG-MT-V Encoder produces compressed JPEG images and the video payload for Motion-JPEG container formats. It accepts images with up to 12-bit color samples and up to four color components, in all widely-used color subsampling formats. Depending on its configuration, the encoder processes from two to 32 color samples per clock cycle, enabling it to compress UHD (4K/8K) video and/or very high frame vid- eo. Once programmed, the easy-to-use encoder requires no assistance from a host pro- cessor to compress an arbitrary number of frames. SoC integration is straightforward thanks to standardized AMBA® interfaces: AXI Streaming for pixel and compressed da- ta, and a 32-bit APB slave interface for registers access. Users can optionally insert timestamps or other metadata in the compressed stream using a dedicated AXI Stream- ing interface.   Introduction
Ultra-low Power Voltage Reference in 40 nm (VVR060LT040) By Quotes None None 40 nm  
Voltage Reference for Integrated PMU (Silicon-proven 40 nm, low-power for IoT with quiescent current of <0.9 μA) This series of fully-integrated low power voltage references generates a 0.6 V output voltage and supports an input from 2.8 to 4.2 V. They operate at an ultra-low quiescent current of < 0.9 μA. These voltage references are silicon-proven in a 40 nm process and are a part of our 40 nm integrated power management unit (PMU) IP core series that has been optimized for integration into Application Specific Integrated Circuits (ASICs) or Systems-on-a-Chip (SoCs), including radio frequency (RF), wireless, and narrowband Internet of Things (NB-IoT) applications. Introduction
Ultra-High Accuracy Bandgap Reference in 130 nm (VBRS1000NT130) By Quotes None None 130 nm  
ACCUREF™ Bandgap Reference (Silicon-proven 40 nm, low-power, low-noise, ultra-precise single-digit mV accuracy, no external components required) ACCUREF™ Voltage and Current References: This series of low-power, low-noise IP cores generates a precise, adjustable reference voltage with single-digit millivolt (mV) accuracy over a wide temperature range without external components. With their unique design that improves upon current products by allowing the systems to operate with ultra-low levels of power consumption without sacrificing accuracy or noise performance, our family of ACCUREF™ voltage and current reference IP cores support a broad range of industry applications with improved efficiency and remarkable area savings overall. Introduction
3 mA Capless LDO in 40 nm (VLDS0003LNT040) By Quotes None None 40 nm  
Power Quencher® Capless LDO (Silicon-proven 40 nm, 3 mA, excellent quiescent current for IoT) This series of low-power, fully-integrated low dropout (LDO) voltage regulators achieves a low-noise output voltage without external components, thus saving package pins and valuable PC board space. These LDOs are silicon-proven in a 40 nm process and are a part of our 40 nm integrated power management unit (PMU) IP core series that has been optimized for integration into Application Specific Integrated Circuits (ASICs) or Systems-on-a-Chip (SoCs), including radio frequency (RF), wireless, and narrowband Internet of Things (NB-IoT) applications. Introduction
High-Accuracy Bandgap Reference in 40 nm (VBR120T040) By Quotes None None 40 nm  
Bandgap Reference for Integrated PMU (Silicon-proven 40 nm, high-accuracy of < ±1%) This series of fully-integrated high-accuracy bandgap voltage references generates a 1.2 V output voltage and supports an input from 2.8 to 4.2 V. They provide an output voltage accuracy of < ±1%. These bandgap references are silicon-proven in a 40 nm process and are a part of our 40 nm integrated power management unit (PMU) IP core series that has been optimized for integration into Application Specific Integrated Circuits (ASICs) or Systems-on-a-Chip (SoCs), including radio frequency (RF), wireless, and narrowband Internet of Things (NB-IoT) applications. Introduction
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