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Sigma-Delta Stereo CODEC in 55nm By Quotes 562.800 K μm^2 96 KHz 55 nm  
The IP is a high resolution, single-chip stereo CODEC that employs the Sigma-Delta noise shaping technique for 55nm logic process. The ADC, DAC and power amplifier are integrated in it. With 18bit resolution for DAC and 18bit resolution for ADC, The IP is suitable for applications in consumer digital audio systems, automobile audio, multimedia and digital systems. Introduction
Digital Video overlay module By Quotes None 250 MHz None  
This IP is a highly versatile video multiplexer that allows one video stream to be inserted over another.  By cascading a series of video overlay modules together, any number of video sources may be multiplexed together. The module supports input video streams of any resolution or aspect ratio up to 216   x 216  pixels in size. Video overlay parameters may be changed on a frame-by-frame basis to dynamically change the size and position of the video overlay. Pixels and syncs flow in and out of the video overlay module in accordance with the valid-ready pipeline protocol. The pipeline protocol allows both input and output interfaces to be stalled independently. In addition, the overlay module supports a number of blending operations including an 8-bit alpha channel and bitwise AND, OR and XOR functions. Application Network and Tactical operations centres Digital-video special effects Broadcast TV and film production CCTV and security camera systems Introduction
2D Graphics Overlay By Quotes None 200 MHz None  
This is a highly versatile on-screen display that allows high-quality anti-aliased bitmap graphics to be inserted over RGB video. The module supports a wide range of graphics effects and the programming interface is very simple to use. The bitmap overlay is partitioned into an array of tiles which are addressed by means of an 8-bit value stored in a 64x64 tile buffer. There are four tile sizes available - either 8x8, 16x16, 32x32 or 64x64. The tiles in the buffer are displayed in a graphics window which may be positioned anywhere within the display area. Bitmaps for each tile are stored in a user-defined ROM which can contain up to  256  different bitmaps stored over three bit-planes. Depending on the chosen graphics mode, the 3-bits per pixel may be used to select one colour from a palette of eight, eight levels of alpha transparency or seven colours on a transparent background. Pixels and syncs flow in and out of the overlay module in accordance with the valid-ready pipeline protocol. Application Animated 2D graphics including hardware sprites, mouse pointers, cursors , parallax scrolling, moving banners etc. Interactive guides, menus, tables, lists etc. Digital TV and home-media solutions Professional and functional 2D graphic displays and video overlays   Introduction
Text Overlay Module By Quotes None 200 MHz None  
The IP Core is a highly versatile On Screen Display (OSD) module that allows text and bitmap graphics to be inserted over RGB video.   The module supports a wide range of text effects and the programming interface is very simple.  Text is written to a 64x32 character buffer which is mapped (via a bitmap ROM) directly to the display. The characters in the buffer are displayed in a 'TEXT BOX' which may be positioned anywhere in the video display area. Bitmaps for each character are stored in a ROM which may be modified to support different font styles or bitmap graphics. Pixels and syncs flow in and out of the overlay module in accordance with the valid-ready pipeline protocol.  Application Window movement in the same manner as a 2D 'BitBlt' Terminal and Console windows Low cost text and graphics applications Digital TV and home-media solutions Introduction
Bilinear Video Scaling Engine By Quotes None 250 MHz None  
This IP is a very high quality video scaler capable of generating interpolated output images from 16x16 up to 216  x 216  pixels in resolution. The architecture permits seamless scaling (either up or down) depending on the chosen scale factor. Internally, the scaler uses a 24-bit accumulator and a bank of polyphase FIR filters with 16 phases or interpolation points.  All filter coefficients are programmable, allowing the user to define a wide range of filter characteristics. Pixels flow in and out of the scaling engine in accordance with the valid-ready pipeline protocol.As such, the pipeline protocol allows both input and output interfaces to be stalled independently. The scaler is partitioned into a horizontal scaling section in series with avertical scaling section. Application Conversion of popular video formats to any other resolution such as VGA to XGA, SVGA to HD1080 etc. Picture in Picture (PiP) applications High quality 24-bit RGB/YCbCr video scaling     Introduction
Digital Video Scaler By Quotes None 250 MHz None  
The IP Core is a studio  quality video scaler capable  of generating interpolated output images from 16 x 16 up to  216  x 216  pixels in resolution.   The architecture permits seamless scaling (either up or down) depending on the chosen scale factor.  Internally, the scaler uses a 24-bit accumulator and a bank of polyphase FIR filters with 16 phases or interpolation points.  All filter coefficients are programmable, allowing the user to define a wide range of filter characteristics. Pixels flow in and out of the video scaler in accordance with the valid-ready pipeline protocol.  Pixels are transferred into the scaler on a rising clock-edge when pixin_val  is high and pixin_rdy is high.  As such, the pipeline protocol allows both input and output interfaces to be stalled independently. The scaler is partitioned into a horizontal scaling module in series with a vertical scaling module . Application Support for the latest generation video formats with resolutions of 4K and above Video scaling for flat panel displays, portable devices, video consoles, video format converters, set-top boxes, digital TV etc. Conversion of all standard and custom video resolutions such as HD720P to HD1080P, XGA to VGA etc.   Introduction
USB 3.0 PHY in 110nm By Quotes 1.000 M μm^2 25 MHz 110 nm  
The IP is a high speed SERDES macro which complies with USB3.0 electrical interface specification.  This macro can be easily fabricated to form multiple lanes and implemented in USB systems design, both Host and Device.The  IP is supported USB3.0 Super Speed (5Gbps) protocol and data rate. Introduction
Half-band Nyquist decimation filter By Quotes None 300 MHz None  
This is a polyphase decimation filter that permits the down-sampling of an input signal by any power of 2. The filter core is organized as a highly optimized systolic array, allowing the user to specify very large decimation factors while keeping resource costs to a minimum.   Input data is sampled on the rising clock-edge of clk when CLK_EN  is active high. Internally, the samples are filtered and decimated then presented at the output interface, Y_OUT.The output signal EN_OUT is the output clock-enable signal that indicates when an output sample is valid.   Application Decimation by a wide range of factors from 2 to 2N Reduction of input sample rate to make subsequent signal processing easier Decimation of signals after digital-down-conversion     Introduction
N-channel multiplexed FIR filter By Quotes None 500 MHz None  
The IP is an N-channel multiplexed FIR filter designed for high sample rate  applications  where  hardware  resources  are  limited. The main filter core is organized as a scalable systolic array permitting the user to specify large order filters without compromising maximum attainable clock-speed.   Essentially the filter functions as if it were 'N' separate FIR filters.  Each input sample is multiplexed into the filter at a sample rate equal to Fs /N,  where Fs is the sampling frequency of the main filter core.   Likewise, output samples are updated at a frequency of  Fs /N.   The first sample into the filter is aligned by asserting the signal X_VALID high. The signal  Y_VALID_val  is asserted with the first valid output sample. Data samples are advanced in the pipeline on the rising clock-edge of clk when en is active high.  When en is low then all data samples are stalled.  The clock-enable signal may be used to temporarily disable the filter - or possibly to modify the effective sampling frequency of the system clock.  If the clock-enable is not needed it is recommended that this signal be tied high as it will improve overall circuit performance.   Application Dual-channel inputs such as complex valued I/Q in digital communications systems High-speed filtering applications where hardware resources are limited General purpose FIR filters with odd or even numbers of taps Introduction
FIR filter By Quotes None 300 MHz None  
FIR_F is an FIR filter implementation designed for very high sample rate applications.   Organized as a systolic array the filter is modular and fully scalable, permitting the user to specify large order filters without compromising maximum attainable clock-speed.  Mathematically, the filter implements the difference equation: y[n] = h0 x[n] + h1 x[n−1] + ... + hN x[n−N ] In the above equation, the input signal is x[n], the output signal is y[n] and h0 to hN represent the filter coefficients.  The number N is the filter order, the number of filter taps being equal to N+1.   Application General purpose FIR filters with odd or even numbers of taps Filters with arbitrary sets of coefficients Very high-speed filtering applications Introduction
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