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JPEG Encoder By Quotes None 250 MHz 130 nm  
This IP core has been developed to be a complete standards compliant JPEG / MJPEG Hardware Compressor / Encoder. The data interfaces in the JPEG Encoder IP Core (JPEGE) use the AXI industry standard. The Master I/O data interfaces use an AXI3 bus, forward compatible with AXI4 interconnects. In order to let you assess the properties of the on-the-fly selectable quality setting, please use the slider below the image in order to see the final compressed image and compression ratio. The JPEG Encoder IP Core has a real throughput of two compressed pixels every three clock cycles at any compression ratio for a chroma subsampling of 4:2:0. To calculate the throughput for your platform. Introduction
H.264 Encoder IP Core By Quotes None 150 MHz None  
This H.264 Encoder IP core has been developed to be the highest throughput standards compliant hardware H.264 video compressor.  The IP offers two encoder variants to meet the different targets of features.   The IP include 2 mode. H264E-I: H.264 encoder compliant with CAVLC 4:4:4 Intra Profile (all frames are keyframes)​         The IP core is smaller but yields less compression. It does not require external memory. H264E-P: H.264 encoder compliant with High 4:4:4 Predictive Profile:   The IP core is larger but offers a significantly better compression. Both share the same outstanding processing speed of more than 5.2 pixels encoded per cycle. The data interfaces in the H.264 Encoder IP Core use the AXI industry standard.  The Master I/O data interfaces use an AXI3 bus, forward compatible with AXI4 interconnects. Introduction
Video and Audio develop platform By Quotes None None None  
Single Chip Solution 32-bit RISC MCU SPI/UART/I2C/GPIO Video Process Engine Video DAC/Audio DAC USB 2.0 Video Scaler DDR4 Easy Integrated Customer’s Logic ​Application DVR and POS DVR ATM machine surveillance Home stay monitoring Multiple channel IP camera Introduction
Binary FSK Demodulator By Quotes None 200 MHz None  
This IP is a precision Binary-FSK Demodulator IP Core based on a non-coherent receiver design.  The demodulator is fully programmable, allowing   for   a   varied   range   of   symbol   rates   and   mark/space tone frequencies. Input data samples may be either complex or real for support of either passband or baseband signals.  The module allows easy connectivity to an external ADC with up to 16-bit signed input samples.   Applications: Short range telemetry Software radio Introduction
2.4G PLL(UMC 28nm HPC) By Quotes 24.000 K μm^2 2.4 GHz 28 nm  
Clock output 2.4GHz Input clock 10 ~ 50MHz Current consumption: < 4mA Supply: 1.8V / 0.9V UMC 28nm HPC Introduction
High-speed FIR Filter with symmetry By Quotes None 500 MHz None  
This IP is an FIR filter IP Core with symmetrical coefficients and an even or odd number of filter taps. The architecture exploits the symmetry of the coefficients using half the number of   multipliers compared to a normal FIR implementation. The result is a filter with a reduced area footprint while still maintaining the capacity for high sample rates.   Application High-speed filter applications where resources are limited General purpose FIR filters with symmetrical coefficients   Introduction
IIR filter Second-Order By Quotes None 150 MHz None  
This IP is a second order IIR filter sometimes referred to as a 'bi-quad'. Internally,   it   has   a   fully   pipelined   architecture   permitting   the   highest possible sample rates for IIR filtering.    Values are sampled on the rising clock-edge of clk when EN is high.  The latency of the IIR filter between the first input sample and the first output sample is 7 clock cycles.    Applicaion IIR filtering in higher sample-rate applications General purpose high-pass, band-pass and low-pass filters Introduction
Color-space Converter By Quotes None 400 MHz None  
This  IP  is a fully pipelined color-space converter that converts pixels between the RGB and YCbCr color spaces.  In total, the IP Core package contains two distinct modules – one module that converts   from   24-bit   RGB   to   30-bit   4:4:4   YCbCr   and   the   other   that performs the reciprocal operation from 4:4:4 YCbCr to RGB.   Application Digital video and image processing  Introduction
ITU-R BT.656 video decoder By Quotes None 300 MHz None  
DEC_BT656 is a digital video decoder with integrated colour-space converter.  It's function is to extract the valid pixels from a BT.656 video stream and convert them to 24-bit RGB for subsequent processing. Pixels   are   extracted   from   the   BT.656   input   stream   and   converted   to RGB888 format.    Application  BT.656 input video capture and processing PAL & NTSC SDTV interlaced format conversion Introduction
ITU-R BT.656 video encoder By Quotes None 200 MHz None  
ITU-R_BT is a digital video encoder with integrated colour-space converter.   The encoder accepts 24-bit RGB pixels from sequential odd and even fields.   These pixels are then mapped to the YCbCr colour-space and formatted correctly into a BT output stream. The output of the encoder generates an industry standard ITU-R BT.656 format video stream together with a video_val signal that is asserted with the first valid byte of the output stream.   Applications BT.656 output video generation PAL & NTSC SDTV video format conversion   Introduction
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