USB2.0 UTMI Device PHY(non-oscillator) 100000 Points 280.000 K μm^2 30.6 MHz 40 nm 2017/06/20
The USB PHY is an UTMI compatible USB2.0 device PHY IP which does not  require external oscillator reference. It is comprised of both USB1.1 and USB2.0  transceivers and it is also comprised of digital logic needed to convert USB serial  data to 8 or 16 bit parallel data. Introduction
NVM test and repair 60000 Points 5.250 K Gates 2.2 GHz 40 nm 2017/06/05
HEART (High Efficient Accumulative Repairing Technical) is a built-in self-repair (BISR) mechanism which uses to recover errors detected after memory testing and to improve yield rate. This mechanism is implemented with spare memories and a built-in redundancy analyze (BIRA) logics which is designed to allocate the redundancy. It needs a storable device (eFuse, OTP or registers) to store testing results after analysis. We provides an efficient accumulative repairing solution to combine advantages of soft BISR mechanism and hard BISR mechanism for improving yield rate. Introduction
HEART(High Efficient Accumulative Repairing Technical) 50000 Points 5.250 K Gates 2.2 GHz 40 nm 2017/06/05
HEART can efficient repair faulty SRAM after using BRAINS. SoCs can mantain correctness of functions and avoid fatal error of system reault in SRAM's defect through SRAM's repairing technical. HEART is SRAM accumulative repairing technical, and it combines advantages of Soft-repair and Hard-repair. HEART supports internal registers of SoCs and external storages of SoCs to record SRAM's faulty information. Once SoCs have new SRAM's defect after using them for a long time, users can repeated repair SRAM's defect through HEART. In addtion, HEART also support "On-Demad" testing and repairing requirement. It means that users can enable system registers of SoCs or signal of HEART to test and repair SRAM at one when SoCs have fatal error situations.   Introduction
BRAINS 50000 Points 5.250 K Gates 1.2 GHz 40 nm 2017/06/05
With improvement of technology node and IC design is geting more complex, the ratio of embedded memory in SoCs have been exceeding 50%. The fault types of memory are getting complex. The Memory BIST (Built-In Self-Test) is generated for efficient controlling IC cost. The traditional BIST method is inserted along with single memory. If there are many memories in SoCs, the area and testing time of SoCs are expanded a lot due to insertion of BIST. Therefore the SoCs' cost will increase rapidly because memory testing time is too long.  We devoted in developing SRAM testing solutions for a long time. BRAINS is based on memory testing patents to reduce testing time and increase yield rate. In addition, BRAINS has many unique features to increase SoCs' reliability and stability.   Introduction
USB2.0 OTG PHY in 40 nm 80000 Points 257.556 K μm^2 30.6 MHz 40 nm 2017/06/19
The IP is an UTMI+ Level 3 compatible USB2.0 OTG function  transceiver IP. It is comprised of both USB1.1 and USB2.0 transceivers; itis  comprised of digital logic needed to convert USB serial data to 8 or 16 bit parallel  data for high speed and full speed. It is also support full speed and low speed  serial mode. Introduction
12-Bit 800KSPS Low Power SAR-ADC By Quotes None 25 MHz 180 nm 2017/07/08
The SAR-ADC is a low power ADC that is implemented in Successive Approximation architecture. It can provide 12-bit resolution capability with only 3V supply voltage. It accepts an analog input range from 0 to VCC   and digitizes the input at a maximum sampling frequency rate of 800KHz at 5V supply voltage. This ADC also includes MUX design to select 0 of 7 analog inputs. The power dissipation is less than 5mW with 5V power supply. This SAR-ADC is implemented in SMIC 0.18μm generic CMOS technology. Introduction
Low power oscillator 12000 Points 100.100 μm^2 32 KHz 40 nm 2017/06/08
OSC32K is designed for 40nm advance process with 1.2v to 3.3v wide power(VDD) range.    Introduction
12-Bit 320MPS IQ DAC 30000 Points 250.000 K μm^2 320 MHz 180 nm 2016/12/20
UIP_DAC12X2_320M_922687  is  compact  and low  power  12-bit  digital-to-analog  converter silicon  IP  in  IBM  180nm  SOI  process.  It features two channel current steering DAC.  This  IQ  DAC  IP  is  optimized  for  low  power and  small  area.  At  320  MHz  conversation rate,  it  only  consumes  63mW  and  occupies silicon area of 0.25 mm2.   APPLICATIONS​ WiFi / LTE / WiMax​ Wireless MIMO Digital Video Communication Transmit   Introduction
14 Bit Rail to Rail DAC 30000 Points 75.000 K μm^2 1 MHz 110 nm 2016/11/21
UIP_DAC14_1M_392231  is  compact  and  low power 14-bit digital-to-analog converter silicon IP. It features wide range input supply voltage from  1.7V  to  5.6V.  Its  single-end  output ranges from 0.1 to 0.9 of supply voltage.     This DAC IP is self-biased and optimized for low  power  and  small  area.   At 1 MHz conversation rate, it only consumes 680uA to drive  15K/50pF  loading  and  occupies  silicon area of 0.075 mm2.   APPLICATIONS General purpose digital to analog converter Battery monitory system Housekeeping Auxiliary functionality Introduction
14-Bit 3 MSPS ADC in GSMC110nm 30000 Points 32.000 K μm^2 3 MHz 110 nm 2016/11/14
UIP_ADC14_3M_245303  is  compact  and  low power 14-bit analog-to-digital converter silicon IP.  It  has  20  single-end  input  channel selection  multiplexer  or  10  differential  input channels  selection.  This  ADC  uses  fully differential SAR architecture optimized for low power and small area. The ADC is designed for  high  dynamic  performance  for  input frequencies  up  to  Nyquist  rate.  This  ADC consumes  150  uA  at  3  MSPS  operation  and occupies  silicon  area  of  0.32 mm2 .  The  ADC has  high  immunity  to  substrate  noise  and  is ideal  for  SoC  integration.   APPLICATIONS  General purpose data acquisition Battery monitory system  Temperature monitory system Introduction
μIP Price Logic Gate Count Clock Rate Technology Released Date Ratings

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