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Delta sigma DAC 24bit 20000 Points 2018/07/05 2018/11/30
The IP has stereo digital-to-analog output systems including interpolation, multibit D/A conversion and  output  analog  filtering .  The IP supports major audio data interface formats.  Individual  devices  differ  only  in  the  supported interface format. The IP is based on a fourth-order multibit delta-sigma modulator with a linear analog low-pass filter. This IP also includes autospeed mode detection using  both  sample  rate  and  master  clock  ratio  as  a method of auto-selecting sampling rates between 2 kHz and 200 kHz. The IP contains on-chip digital deempha-sis, operates from a single +3.3 V or +5 V power supply,and requires minimal support circuitry. These features are  ideal  for  DVD  players  &  recorders,  digital  televisions,  home  theater  and  set  top  box  products,  and automotive audio systems. Introduction
8b/10b Encoder/Decoder 800 Points 2015/03/31 2015/11/01
● Supports the standard IBMR 8b/10b line code for a        DC-balanced serial data stream   ● Supports all standard control symbols - K.28.0 to K.30.7   ● Fully synchronous design with data input and output valid flags   ● Separate encoder and decoder pair   ● Error flags indicate control symbol errors and general decoding errors   ● Generic parallel input and output data widths   ● Synthesis constraint for Design code   ● Running disparity calculations handled internally Introduction
8051 IP Core 1000 Points 2014/10/28 2015/05/01
(1) 100% software compatible with industry standard 8051 (2)  Advanced architecture enables to execute instructions on average 4~1 times       faster compared to original 8051 (3)  Fully synthesizable synchronous design with positive edge clocking and       no internal tri-state (4) Two 16-bit timer/counters for interrupt (5) Two external interrupts (6) Simulation & synthesis scripts (7) Self checking testbench Introduction
Query Result
Wanted μIP Wanted Payment Post Date Deadline