OUTSOURCING DEMAND Add to My Favorite

  • μIP NO.: 426887920
  • μIP Type: Mixed μIP
  • Wanted μIP: Amplitude Shift Keying Receiver and Transmitter
  • HDL: Verilog Behavioral Model
  • Wanted Design Format: GDS or Schematic
  • Simulation Tool: Cadence NC-Verilog
  • Tool Version:
  • Post Date: 2015-07-10
  • Deadline: 2016-08-20
  • Wanted Payment: 30000 Points
  • Sharing Mechanism: YES
  • Share Ratio: 5%
    Wanter Information
  • Member ID: 3790449000600388
  • Number of Wanted Posted: 1
  • Number of Try Run:0
  • Number of Successful Transaction:0

1. Description:

The IP is a general purpose,ASK (Amplitude Shift Keying) Receiver that operates at 300-450MHz with typical senditivity of -98dBm.The IP functions as a super-heterodyne receiver for OOK and ASK modulation up to 10kbps.The down-coversion mixer also provides image rejection.All post-detection data filtering is provided on the IP.Any one-of-four filter bandwidths may be selected externally by the user in binary steps,from 1.25KHz to 10KHz.

The user need only configure the device with a set of easily determined values,based upon data rate,code modulation format, and desired duty-cycle operation.

 

  • -98 dBm sensitivity,1kbps and BER 10E-02
  • Frequency from 300MHz to 450MHz
  • Image Rejection Mixer Data-rate up to 10kbps
  • Process from 0.35um to 0.13um
  • Need Receiver and Transmitter module
 

2. Clock Rate:

non-limit 

3. Area:

non-limit 

4. Technology:

non-limit