(Thanks to the Taiwan’s Commercial Times for the Coverage)


As semiconductor processes enter the 2nm era, James Yang, Chairman of MicroIP, pointed out that the difficulty of IC design has increased sharply. In the future, the roles of silicon intellectual property (IP) and ASIC will become more critical, helping IC design respond to the new AI generation in the form of SoCs. James Yang analyzed that the paradigm shift from IDM splitting to foundry will occur in IC design, and the trend of large-scale IC design becoming dominant in the AI era is taking shape.

MicroIP has already received outsourced AI chip orders from major international chip manufacturers. James Yang believes that with chip transistors now numbering in the tens of billions, IC design companies’ R&D capabilities are being tested. By extensively adopting foundational and interface IPs, R&D capabilities can focus more on front-end design. Overseas manufacturers are even outsourcing back-end design to ASIC companies, and the future reliance on IP and ASIC trends will only become more apparent.

Taiwan’s semiconductor industry chain holds a leading global position in logic advanced processes, advanced packaging, and 3D IC technology, enhancing the overall industry’s visibility. James Yang further analyzed that starting from advanced processes, international giants’ demand for high-performance computing hardware relies on Taiwanese companies for back-end design assistance. MicroIP has already secured outsourcing orders from major international chip manufacturers. Key algorithms are mastered by the companies themselves, while MicroIP assists in creating the surrounding bare chips (DIE).

The rise of AI signifies massive demand for chips driven by large-scale applications. James Yang emphasized that AI is shaping a new landscape in semiconductors. Taking MicroIP as an example, entering the field of bare chip (DIE) design from the IP library is driven by customer demand. Both complement each other, and future market demand will only grow larger.

In the era of advanced process chips, the big get bigger, and there is a variety of low-volume production. Small and medium-sized companies find it difficult to achieve significant success with a single chip. James Yang admitted that having key IP and ASIC technology is the way for Fabless companies to continue growing. James Yang is also leading the team into the EDA field, creating an ecosystem, providing front-end verification services for chips, and further extracting more value in the semiconductor field.

James Yang revealed that with the development of advanced packaging and CoWoS, future 3D stacking and thermal analysis will be critical battlegrounds. Through heterogeneous integration, different process chips can be integrated, and even SoCs can be created using different foundries.